Scale-invariant feature transform (SIFT) includes complex computations that require hardware implementation for real-time operations. Previous works on SIFT hardware acceleration used a large amount of internal memory, which limited a wider use of SIFT. This paper proposes a new SIFT hardware architecture that significantly reduces the amount of required internal memory by storing temporary data into external memory. The use of external memory demands an excessive bandwidth (BW) for the external memory. In order to reduce the external memory BW, this paper proposes three schemes: 1) local-patch reuse; 2) local-patch subsampling; and 3) fraction-bit truncation. As a result, the proposed hardware processes High Definition (HD)-sized (1280 × 720) video at 36.85 frames/s with an external memory BW of 2.37 B/cycle and an internal memory of 396.03 kbits, which are acceptable for practical use with various applications. This is achieved because the external memory access is reduced to only 4.75% of that without the proposed schemes and also because the size of the internal memory is reduced to 10.93% compared with the size required in the previous work.
|Number of pages||12|
|Journal||IEEE Transactions on Circuits and Systems for Video Technology|
|Publication status||Published - 2016 Oct|
Bibliographical noteFunding Information:
This work was supported in part by Samsung Electronics and in part by the Ministry of Science, ICT and Future Planning, Korea, through the Information Technology Research Center support Program under Grant IITP-2015-H8501-15-1005 supervised by the Institute for Information and Communications Technology Promotion.
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering