A novel method for forming gate spacer and its effects on the W/WN x/Poly-si gate stack

Yong Soo Kim, Kwan Yong Lim, Jae Geun Oh, Se Aug Jang, Heung Jae Cho, Jun Mo Yang, Jai Bum Suh, Su Ock Chung, Soo Young Park, Hong Seon Yang, Hyun Chul Sohn, Jin Woong Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A novel method for forming the SiO2/Si3N4 (O/N) gate spacer has been developed through applying the low temperature atomic layer deposition (ALD) SiO2 film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird's beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at same Vt, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.

Original languageEnglish
Title of host publicationESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference
EditorsR.P. Mertens, C.L. Claeys
Pages97-100
Number of pages4
Publication statusPublished - 2004
EventESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference - Leuven, Belgium
Duration: 2004 Sep 212004 Sep 23

Publication series

NameESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Other

OtherESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference
CountryBelgium
CityLeuven
Period04/9/2104/9/23

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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