A novel method for forming gate spacer and its effects on the W/WN x/Poly-si gate stack

Yong Soo Kim; Kwan Yong Lim; Jae Geun Oh; Se Aug Jang; Heung Jae Cho; Jun Mo Yang; Jai Bum Suh; Su Ock Chung; Soo Young Park; Hong Seon Yang; Hyun Chul Sohn; Jin Woong Kim

A novel method for forming gate spacer and its effects on the W/WN _x/Poly-si gate stack

Yong Soo Kim, Kwan Yong Lim, Jae Geun Oh, Se Aug Jang, Heung Jae Cho, Jun Mo Yang, Jai Bum Suh, Su Ock Chung, Soo Young Park, Hong Seon Yang, Hyun Chul Sohn, Jin Woong Kim

Department of Materials Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A novel method for forming the SiO₂/Si₃N₄ (O/N) gate spacer has been developed through applying the low temperature atomic layer deposition (ALD) SiO₂ film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird's beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at same Vt, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.

Original language	English
Title of host publication	ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference
Editors	R.P. Mertens, C.L. Claeys
Pages	97-100
Number of pages	4
Publication status	Published - 2004
Event	ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference - Leuven, Belgium Duration: 2004 Sept 21 → 2004 Sept 23

Publication series

Name	ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Other

Other	ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference
Country/Territory	Belgium
City	Leuven
Period	04/9/21 → 04/9/23

All Science Journal Classification (ASJC) codes

Engineering(all)

Cite this

Kim, Y. S., Lim, K. Y., Oh, J. G., Jang, S. A., Cho, H. J., Yang, J. M., Suh, J. B., Chung, S. O., Park, S. Y., Yang, H. S., Sohn, H. C., & Kim, J. W. (2004). A novel method for forming gate spacer and its effects on the W/WN _x/Poly-si gate stack. In R. P. Mertens, & C. L. Claeys (Eds.), ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference (pp. 97-100). (ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference).

Kim, Yong Soo ; Lim, Kwan Yong ; Oh, Jae Geun et al. / A novel method for forming gate spacer and its effects on the W/WN _x/Poly-si gate stack. ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference. editor / R.P. Mertens ; C.L. Claeys. 2004. pp. 97-100 (ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference).

@inproceedings{b30b75981e124bb8bf016ec699953d13,

title = "A novel method for forming gate spacer and its effects on the W/WN x/Poly-si gate stack",

abstract = "A novel method for forming the SiO2/Si3N4 (O/N) gate spacer has been developed through applying the low temperature atomic layer deposition (ALD) SiO2 film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird's beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at same Vt, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.",

author = "Kim, {Yong Soo} and Lim, {Kwan Yong} and Oh, {Jae Geun} and Jang, {Se Aug} and Cho, {Heung Jae} and Yang, {Jun Mo} and Suh, {Jai Bum} and Chung, {Su Ock} and Park, {Soo Young} and Yang, {Hong Seon} and Sohn, {Hyun Chul} and Kim, {Jin Woong}",

year = "2004",

language = "English",

isbn = "0780384784",

series = "ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference",

pages = "97--100",

editor = "R.P. Mertens and C.L. Claeys",

booktitle = "ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference",

note = "ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference ; Conference date: 21-09-2004 Through 23-09-2004",

}

Kim, YS, Lim, KY, Oh, JG, Jang, SA, Cho, HJ, Yang, JM, Suh, JB, Chung, SO, Park, SY, Yang, HS, Sohn, HC & Kim, JW 2004, A novel method for forming gate spacer and its effects on the W/WN _x/Poly-si gate stack. in RP Mertens & CL Claeys (eds), ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference. ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference, pp. 97-100, ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference, Leuven, Belgium, 04/9/21.

A novel method for forming gate spacer and its effects on the W/WN _x/Poly-si gate stack. / Kim, Yong Soo; Lim, Kwan Yong; Oh, Jae Geun et al.

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference. ed. / R.P. Mertens; C.L. Claeys. 2004. p. 97-100 (ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A novel method for forming gate spacer and its effects on the W/WN x/Poly-si gate stack

AU - Kim, Yong Soo

AU - Lim, Kwan Yong

AU - Oh, Jae Geun

AU - Jang, Se Aug

AU - Cho, Heung Jae

AU - Yang, Jun Mo

AU - Suh, Jai Bum

AU - Chung, Su Ock

AU - Park, Soo Young

AU - Yang, Hong Seon

AU - Sohn, Hyun Chul

AU - Kim, Jin Woong

PY - 2004

Y1 - 2004

N2 - A novel method for forming the SiO2/Si3N4 (O/N) gate spacer has been developed through applying the low temperature atomic layer deposition (ALD) SiO2 film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird's beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at same Vt, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.

AB - A novel method for forming the SiO2/Si3N4 (O/N) gate spacer has been developed through applying the low temperature atomic layer deposition (ALD) SiO2 film. Using this scheme, the Si-O rich interfacial dielectric layer formation and the metal (W) contamination caused by the selective oxidation (SO) process were controlled. Our technique also suppresses the thickness increase of the gate oxide during the SO and enhances the rounding of gate bird's beak (GBB) at the gate edges. Furthermore, the O/N gate spacered device exhibits less junction leakage currents, about 1 order of magnitude lower gate induced drain leakage (GIDL) currents at same Vt, and better hot carrier degradation (HCD) immunity compared to the N/O/N gated spacer device.

UR - http://www.scopus.com/inward/record.url?scp=20244385962&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20244385962&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:20244385962

SN - 0780384784

T3 - ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

SP - 97

EP - 100

BT - ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

A2 - Mertens, R.P.

A2 - Claeys, C.L.

T2 - ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Y2 - 21 September 2004 through 23 September 2004

ER -

Kim YS, Lim KY, Oh JG, Jang SA, Cho HJ, Yang JM et al. A novel method for forming gate spacer and its effects on the W/WN _x/Poly-si gate stack. In Mertens RP, Claeys CL, editors, ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference. 2004. p. 97-100. (ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference).