Solid-state drive (SSD) has become one of the most dominant storage devices and is rapidly replacing conventional storage devices. The core component of SSD is NAND flash memory (NFM), where the actual data are stored. Cost pressure is the most critical factor limiting the further deployment of SSDs and past researches have focused on developing cost-effective high-density NFM. Although the cost-driven technology development increases per-chip capacity, it reduces channel-/way-level parallelisms for the given device capacity, resulting in the performance degradation. Such observation directs us to focus on a novel NFM architecture exploiting plane-level parallelism. The distinct features of this architecture are: 1) enabling a decoupled word-line (WL) selection for the mated planes and 2) segmenting each plane into subplanes for further maximizing the plane-level parallelism. The experimental results show that decoupled WL selection improves the throughput by up to 21.3% with a marginal overhead of less than 1%, compared to the conventional NFM architecture. In addition, adopting the plane segmentation improves the throughput by up to 43.9% with an additional overhead of 14%. Considering the tradeoff between performance and overhead, the proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2019 Aug|
Bibliographical noteFunding Information:
Manuscript received October 29, 2018; revised January 26, 2019; accepted March 12, 2019. Date of publication April 11, 2019; date of current version July 24, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (2016R1A2B4011799); in part by the MOTIE (Ministry of Trade, Industry & Energy) (10080722) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device; and in part by Samsung Electronics Company, Ltd., Hwaseong, Korea. The EDA tool was also supported by the IC Design Education Center (IDEC), Korea. (Corresponding author: Eui-Young Chung.) M. Kim and E.-Y. Chung are with the School of Electrical and Elec- tronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: email@example.com). W. Jung is with Samsung Electronics Company, Ltd., Hwaseong 18448, South Korea. H.-J. Lee is with the School of Computer Science and Engineering, Sogang University, Seoul 04107, South Korea. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2019.2905626 1Recently, quadruple-level cell (QLC)-based NFM is actively researched. 2Mated planes refer to the physically adjacent planes within a single way. 1063-8210 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering