A novel nand flash memory architecture for maximally exploiting plane-level parallelism

Myeongjin Kim, Wontaeck Jung, Hyuk Jun Lee, Eui Young Chung

Research output: Contribution to journalArticle

Abstract

Solid-state drive (SSD) has become one of the most dominant storage devices and is rapidly replacing conventional storage devices. The core component of SSD is NAND flash memory (NFM), where the actual data are stored. Cost pressure is the most critical factor limiting the further deployment of SSDs and past researches have focused on developing cost-effective high-density NFM. Although the cost-driven technology development increases per-chip capacity, it reduces channel-/way-level parallelisms for the given device capacity, resulting in the performance degradation. Such observation directs us to focus on a novel NFM architecture exploiting plane-level parallelism. The distinct features of this architecture are: 1) enabling a decoupled word-line (WL) selection for the mated planes and 2) segmenting each plane into subplanes for further maximizing the plane-level parallelism. The experimental results show that decoupled WL selection improves the throughput by up to 21.3% with a marginal overhead of less than 1%, compared to the conventional NFM architecture. In addition, adopting the plane segmentation improves the throughput by up to 43.9% with an additional overhead of 14%. Considering the tradeoff between performance and overhead, the proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.

Original languageEnglish
Article number8685794
Pages (from-to)1957-1961
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume27
Issue number8
DOIs
Publication statusPublished - 2019 Aug

Fingerprint

Memory architecture
Flash memory
Costs
Throughput
Degradation

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{acd72fdc2c1647f2b485229f56959f07,
title = "A novel nand flash memory architecture for maximally exploiting plane-level parallelism",
abstract = "Solid-state drive (SSD) has become one of the most dominant storage devices and is rapidly replacing conventional storage devices. The core component of SSD is NAND flash memory (NFM), where the actual data are stored. Cost pressure is the most critical factor limiting the further deployment of SSDs and past researches have focused on developing cost-effective high-density NFM. Although the cost-driven technology development increases per-chip capacity, it reduces channel-/way-level parallelisms for the given device capacity, resulting in the performance degradation. Such observation directs us to focus on a novel NFM architecture exploiting plane-level parallelism. The distinct features of this architecture are: 1) enabling a decoupled word-line (WL) selection for the mated planes and 2) segmenting each plane into subplanes for further maximizing the plane-level parallelism. The experimental results show that decoupled WL selection improves the throughput by up to 21.3{\%} with a marginal overhead of less than 1{\%}, compared to the conventional NFM architecture. In addition, adopting the plane segmentation improves the throughput by up to 43.9{\%} with an additional overhead of 14{\%}. Considering the tradeoff between performance and overhead, the proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.",
author = "Myeongjin Kim and Wontaeck Jung and Lee, {Hyuk Jun} and Chung, {Eui Young}",
year = "2019",
month = "8",
doi = "10.1109/TVLSI.2019.2905626",
language = "English",
volume = "27",
pages = "1957--1961",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

A novel nand flash memory architecture for maximally exploiting plane-level parallelism. / Kim, Myeongjin; Jung, Wontaeck; Lee, Hyuk Jun; Chung, Eui Young.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 8, 8685794, 08.2019, p. 1957-1961.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A novel nand flash memory architecture for maximally exploiting plane-level parallelism

AU - Kim, Myeongjin

AU - Jung, Wontaeck

AU - Lee, Hyuk Jun

AU - Chung, Eui Young

PY - 2019/8

Y1 - 2019/8

N2 - Solid-state drive (SSD) has become one of the most dominant storage devices and is rapidly replacing conventional storage devices. The core component of SSD is NAND flash memory (NFM), where the actual data are stored. Cost pressure is the most critical factor limiting the further deployment of SSDs and past researches have focused on developing cost-effective high-density NFM. Although the cost-driven technology development increases per-chip capacity, it reduces channel-/way-level parallelisms for the given device capacity, resulting in the performance degradation. Such observation directs us to focus on a novel NFM architecture exploiting plane-level parallelism. The distinct features of this architecture are: 1) enabling a decoupled word-line (WL) selection for the mated planes and 2) segmenting each plane into subplanes for further maximizing the plane-level parallelism. The experimental results show that decoupled WL selection improves the throughput by up to 21.3% with a marginal overhead of less than 1%, compared to the conventional NFM architecture. In addition, adopting the plane segmentation improves the throughput by up to 43.9% with an additional overhead of 14%. Considering the tradeoff between performance and overhead, the proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.

AB - Solid-state drive (SSD) has become one of the most dominant storage devices and is rapidly replacing conventional storage devices. The core component of SSD is NAND flash memory (NFM), where the actual data are stored. Cost pressure is the most critical factor limiting the further deployment of SSDs and past researches have focused on developing cost-effective high-density NFM. Although the cost-driven technology development increases per-chip capacity, it reduces channel-/way-level parallelisms for the given device capacity, resulting in the performance degradation. Such observation directs us to focus on a novel NFM architecture exploiting plane-level parallelism. The distinct features of this architecture are: 1) enabling a decoupled word-line (WL) selection for the mated planes and 2) segmenting each plane into subplanes for further maximizing the plane-level parallelism. The experimental results show that decoupled WL selection improves the throughput by up to 21.3% with a marginal overhead of less than 1%, compared to the conventional NFM architecture. In addition, adopting the plane segmentation improves the throughput by up to 43.9% with an additional overhead of 14%. Considering the tradeoff between performance and overhead, the proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.

UR - http://www.scopus.com/inward/record.url?scp=85069970554&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85069970554&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2019.2905626

DO - 10.1109/TVLSI.2019.2905626

M3 - Article

AN - SCOPUS:85069970554

VL - 27

SP - 1957

EP - 1961

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 8

M1 - 8685794

ER -