A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM)

Jisu Kim, Kyungho Ryu, Seung H. Kang, Seong Ook Jung

Research output: Contribution to journalArticle

52 Citations (Scopus)

Abstract

STT-MRAM has emerged as a compelling candidate for universal memory, but demands an advanced sensing circuit to achieve the proper sensing margin. In addition, STT-MRAM requires low-current sensing to avoid read disturbance. We report a novel sensing circuit that utilizes a source degeneration scheme and a balanced reference scheme. Monte Carlo HSPICE simulation results using 65 nm technology model parameters show that the proposed sensing circuit achieves an read access yield of 96.3% with a sensing current of 43.1 uA at a supply voltage of 1.1 V for 32 M bit, whereas the conventional sensing circuit achieves an read access yield of only 0% (81.5%) with a sensing current of 48.0 uA (64.2 uA) at a supply voltage of 1.1 V (1.6 V).

Original languageEnglish
Article number5640700
Pages (from-to)181-186
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number1
DOIs
Publication statusPublished - 2012 Jan 1

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Torque
Networks (circuits)
Electric potential
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM). / Kim, Jisu; Ryu, Kyungho; Kang, Seung H.; Jung, Seong Ook.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 1, 5640700, 01.01.2012, p. 181-186.

Research output: Contribution to journalArticle

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