A novel test access mechanism for parallel testing of multi-core system

Taewoo Han, Inhyuk Choi, Sungho Kang

Research output: Contribution to journalLetter

1 Citation (Scopus)

Abstract

The increased usages of multi-core systems diminish percore complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.

Original languageEnglish
Journalieice electronics express
Volume11
Issue number6
DOIs
Publication statusPublished - 2014 Mar 6

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Hardware
Testing
Costs
Experiments
hardware
costs
output

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

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A novel test access mechanism for parallel testing of multi-core system. / Han, Taewoo; Choi, Inhyuk; Kang, Sungho.

In: ieice electronics express, Vol. 11, No. 6, 06.03.2014.

Research output: Contribution to journalLetter

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AU - Choi, Inhyuk

AU - Kang, Sungho

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AB - The increased usages of multi-core systems diminish percore complexity and also demand several parallel design and test technologies. This paper introduces a novel test access mechanism (TAM) for parallel testing of multiple identical cores. Instead of typical test response data from the cores, the test output data used in this paper are the majority values extracted from the typical test response from the cores. All the cores can be tested in parallel and test costs (test time, test pins) are exactly the same as for a single core. The experiment results in this paper show the proposed TAM can test multiple cores with minimal test pins and test time and with negligible hardware overhead.

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