A pipelined hardware architecture for motion estimation of H.264/AVC

Su Jin Lee, Cheong Ghil Kim, Shin-Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The variable block size motion estimation (VBSME) presented in the video coding standard H.264/AVC significantly improves coding efficiency, but it requires much more considerable computational complexity than motion estimation using fixed macroblocks. To solve this problem, this paper proposes a pipelined hardware architecture for full-search VBSME aiming for high performance, simple structure, and small controls. Our architecture consists of 1-D arrays with 64 processing elements, an adder tree to produce motion vectors (MVs) for variable block sizes, and comparators to determine the minimum of MVs. This can produce all 41 MVs for variable blocks of one macroblock in the same clock cycles to other conventional 1-D arrays of 64 PEs. In addition, this can be easily controlled by a 2-bit counter. Implementation results show that our architecture can estimate MVs in GIF video sequence at a rate of 106 frames/s for the 32×32 search range.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings
Pages79-89
Number of pages11
Volume3740 LNCS
Publication statusPublished - 2005 Dec 1
Event10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 - Singapore, Singapore
Duration: 2005 Oct 242005 Oct 26

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3740 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005
CountrySingapore
CitySingapore
Period05/10/2405/10/26

Fingerprint

Motion Vector
Hardware Architecture
Motion Estimation
Motion estimation
Hardware
Adders
Video Coding
Image coding
Clocks
Computational complexity
Computational Complexity
High Performance
Coding
Cycle
Processing
Estimate
Range of data
Architecture

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Lee, S. J., Kim, C. G., & Kim, S-D. (2005). A pipelined hardware architecture for motion estimation of H.264/AVC. In Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings (Vol. 3740 LNCS, pp. 79-89). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3740 LNCS).
Lee, Su Jin ; Kim, Cheong Ghil ; Kim, Shin-Dug. / A pipelined hardware architecture for motion estimation of H.264/AVC. Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings. Vol. 3740 LNCS 2005. pp. 79-89 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
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Lee, SJ, Kim, CG & Kim, S-D 2005, A pipelined hardware architecture for motion estimation of H.264/AVC. in Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings. vol. 3740 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 3740 LNCS, pp. 79-89, 10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005, Singapore, Singapore, 05/10/24.

A pipelined hardware architecture for motion estimation of H.264/AVC. / Lee, Su Jin; Kim, Cheong Ghil; Kim, Shin-Dug.

Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings. Vol. 3740 LNCS 2005. p. 79-89 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 3740 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lee SJ, Kim CG, Kim S-D. A pipelined hardware architecture for motion estimation of H.264/AVC. In Advances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings. Vol. 3740 LNCS. 2005. p. 79-89. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).