Abstract
Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture.
| Original language | English |
|---|---|
| Pages (from-to) | 41-46 |
| Number of pages | 6 |
| Journal | Microprocessors and Microsystems |
| Volume | 29 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2005 Feb 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence
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A pixel cache architecture with selective placement scheme based on z-test result. / Lee, K. W.; Park, Woo Chan; Kim, Il San; Han, Tack Don.
In: Microprocessors and Microsystems, Vol. 29, No. 1, 01.02.2005, p. 41-46.Research output: Contribution to journal › Article
TY - JOUR
T1 - A pixel cache architecture with selective placement scheme based on z-test result
AU - Lee, K. W.
AU - Park, Woo Chan
AU - Kim, Il San
AU - Han, Tack Don
PY - 2005/2/1
Y1 - 2005/2/1
N2 - Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture.
AB - Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture.
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UR - http://www.scopus.com/inward/citedby.url?scp=10444247467&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2004.05.004
DO - 10.1016/j.micpro.2004.05.004
M3 - Article
AN - SCOPUS:10444247467
VL - 29
SP - 41
EP - 46
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
SN - 0141-9331
IS - 1
ER -