A pixel cache architecture with selective placement scheme based on z-test result

K. W. Lee, Woo Chan Park, Il San Kim, Tack Don Han

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture.

Original languageEnglish
Pages (from-to)41-46
Number of pages6
JournalMicroprocessors and Microsystems
Volume29
Issue number1
DOIs
Publication statusPublished - 2005 Feb 1

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Pixels
Color
Bandwidth
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

Cite this

Lee, K. W. ; Park, Woo Chan ; Kim, Il San ; Han, Tack Don. / A pixel cache architecture with selective placement scheme based on z-test result. In: Microprocessors and Microsystems. 2005 ; Vol. 29, No. 1. pp. 41-46.
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A pixel cache architecture with selective placement scheme based on z-test result. / Lee, K. W.; Park, Woo Chan; Kim, Il San; Han, Tack Don.

In: Microprocessors and Microsystems, Vol. 29, No. 1, 01.02.2005, p. 41-46.

Research output: Contribution to journalArticle

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