Abstract
Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture.
| Original language | English |
|---|---|
| Pages (from-to) | 41-46 |
| Number of pages | 6 |
| Journal | Microprocessors and Microsystems |
| Volume | 29 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2005 Feb 1 |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Computer Networks and Communications
- Artificial Intelligence
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Cite this
Lee, K. W., Park, W. C., Kim, I. S., & Han, T. D. (2005). A pixel cache architecture with selective placement scheme based on z-test result. Microprocessors and Microsystems, 29(1), 41-46. https://doi.org/10.1016/j.micpro.2004.05.004