We present a new rasterization pipeline based on the tiling traversal algorithm, which can reduce considerably the unnecessary processing cycles occurring in pixel processing step. This architecture can perform efficient occlusion culling at an early stage of the rasterization pipeline by retrieving data from the depth-table. In addition, the proposed architecture can reduce memory bandwidth waste caused by fetching texture data that are obscured by performing z-test before texture mapping. Specifically this scheme might cause a consistency problem for the frame memory if more than two fragments have the same pixel address. However, by using a flagging scheme for the pixel cache, it can detect the overlap condition and maintain the consistency. Simulation results show that the proposed architecture can achieve around 34% performance gain, compared with the conventional pre-textured architecture, and around 11%, compared with the conventional post-textured architecture. Proceedings of the 2005 International Conference on Computer Vision, VlSlON'05.