A power efficient cache structure for embedded processors based on the dual cache structure

Gi Ho Park, Kil Whan Lee, Jae Hyuk Lee, Tack Don Han, Shin Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A dual data cache system structure, called a cooperative cache system, is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). These two caches are con- structed with different block sizes as well as associativities. The block size of the TOC is 8bytes and that of the SOC is 32bytes, and the capacity of each cache is 8Kbytes. The cooperative cache system achieves improvement in performance and reduces power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that is going to be manufactured by Samsung Electronics Co. with 0.25m technology.

Original languageEnglish
Title of host publicationLanguages, Compilers and Tools for Embedded Systems - ACM SIGPLAN Workshop LCTES 2000, Proceedings
EditorsJack Davidson, Sang Lyul Min
PublisherSpringer Verlag
Pages162-177
Number of pages16
ISBN (Print)3540417818, 9783540417811
DOIs
Publication statusPublished - 2001
EventACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2000 - Vancouver, Canada
Duration: 2000 Jun 182000 Jun 18

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1985
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

OtherACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, LCTES 2000
CountryCanada
CityVancouver
Period00/6/1800/6/18

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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  • Cite this

    Park, G. H., Lee, K. W., Lee, J. H., Han, T. D., & Kim, S. D. (2001). A power efficient cache structure for embedded processors based on the dual cache structure. In J. Davidson, & S. L. Min (Eds.), Languages, Compilers and Tools for Embedded Systems - ACM SIGPLAN Workshop LCTES 2000, Proceedings (pp. 162-177). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1985). Springer Verlag. https://doi.org/10.1007/3-540-45245-1_11