A practical test scheduling using network-based TAM in network on chip architecture

Jin Ho Ahn, Byung In Moon, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

It may be impractical to have TAM for test usage only in NoC because it causes enormous hardware overhead. Therefore, the reuse of on-chip networks for TAM is very attractive and logical. In network-based TAM, an effective test scheduling for built-in cores is also important to minimize the total test time. In this paper, we propose a new efficient test scheduling algorithm for NoC based on the reuse of on-chip networks. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the test time by about 5 - 20% compared to previous methods. Consequently, the proposed algorithm can be widely used due to its feasibility and practicality.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 10th Asia-Pacific Conference, ACSAC 2005, Proceedings
PublisherSpringer Verlag
Pages614-624
Number of pages11
ISBN (Print)3540296433, 9783540296430
DOIs
Publication statusPublished - 2005
Event10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005 - Singapore, Singapore
Duration: 2005 Oct 242005 Oct 26

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3740 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other10th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2005
CountrySingapore
CitySingapore
Period05/10/2405/10/26

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

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