A prevenient voltage stress test method for high density memory

Jongsoo Yim, Gunbae Kim, Incheol Nam, Sangki Son, Jonghyoung Lim, Hwacheol Lee, Sangseok Kang, Byungheon Kwak, Jinseok Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The most effective acceleration factor of reliability is the high voltage stress. However high electric field generated on thin gate oxide transistors in nanometer technology becomes the uppermost limit. In this paper, an improved voltage stress method for DRAM with the 6F2 structure and the open bit line scheme is proposed to enhance the Early Life Failure Rates (ELFR) and the yield of package test. The proposed method reduces the degradation of transistors caused by a high voltage stress. Experimental results show that the proposed method improves the yield of package test and the characteristic of refresh, and avoids the degradation of transistors using voltage ramp stress (VRS).

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
Pages516-520
Number of pages5
DOIs
Publication statusPublished - 2008 Sep 5
Event4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 - Hong Kong, SAR, Hong Kong
Duration: 2008 Jan 232008 Jan 25

Other

Other4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008
CountryHong Kong
CityHong Kong, SAR
Period08/1/2308/1/25

Fingerprint

Data storage equipment
Transistors
Electric potential
Degradation
Dynamic random access storage
Electric fields
Oxides

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Yim, J., Kim, G., Nam, I., Son, S., Lim, J., Lee, H., ... Kang, S. (2008). A prevenient voltage stress test method for high density memory. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008 (pp. 516-520). [4459605] https://doi.org/10.1109/DELTA.2008.93
Yim, Jongsoo ; Kim, Gunbae ; Nam, Incheol ; Son, Sangki ; Lim, Jonghyoung ; Lee, Hwacheol ; Kang, Sangseok ; Kwak, Byungheon ; Lee, Jinseok ; Kang, Sungho. / A prevenient voltage stress test method for high density memory. Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. pp. 516-520
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Yim, J, Kim, G, Nam, I, Son, S, Lim, J, Lee, H, Kang, S, Kwak, B, Lee, J & Kang, S 2008, A prevenient voltage stress test method for high density memory. in Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008., 4459605, pp. 516-520, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, SAR, Hong Kong, 08/1/23. https://doi.org/10.1109/DELTA.2008.93

A prevenient voltage stress test method for high density memory. / Yim, Jongsoo; Kim, Gunbae; Nam, Incheol; Son, Sangki; Lim, Jonghyoung; Lee, Hwacheol; Kang, Sangseok; Kwak, Byungheon; Lee, Jinseok; Kang, Sungho.

Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 516-520 4459605.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Yim J, Kim G, Nam I, Son S, Lim J, Lee H et al. A prevenient voltage stress test method for high density memory. In Proceedings - 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008. 2008. p. 516-520. 4459605 https://doi.org/10.1109/DELTA.2008.93