Processor power management in handheld devices is the primary technique for exploiting power reduction while ensuring performance. Modern mobile devices require high performance at the system level to decode high-bitrate multimedia. For this reason, processor offloading using off-chip controllers is commonly exercised in this field. However, current power management techniques do not fully consider the offloading architecture. We propose a scheme to achieve power reduction through an empirical method, which detects and classifies off-chip usages, in addition to combining dynamic voltage scaling (DVS) with dynamic power management (DPM). We experimented with the proposed technique in a real hardware environment and achieved up to a 37% power reduction compared with previous schemes.
Bibliographical noteFunding Information:
Manuscript received January 13, 2010; revised March 16, 2010; accepted May 03, 2010. Date of publication June 14, 2010; date of current version August 06, 2010. This work was supported in part by the National Research Foundation (NRF) of Korea under Grant 2009-0079878 and Grant 2009-0066418. Paper no. TII-10-01-0005. J. Choi is with the Application Design Center, Intel Corporation, Seoul 150-705, Korea (e-mail: email@example.com). H. Cha is with the Department of Computer Science, Yonsei University, Seoul 120-749, Korea (e-mail: firstname.lastname@example.org). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TII.2010.2050330
All Science Journal Classification (ASJC) codes
- Control and Systems Engineering
- Information Systems
- Computer Science Applications
- Electrical and Electronic Engineering