TY - GEN
T1 - A re-configurable FTL (Flash Translation Layer) architecture for NAND flash based applications
AU - Park, Chanik
AU - Cheon, Wonmoon
AU - Lee, Yangsup
AU - Jung, Myoung Soo
AU - Cho, Wonhee
AU - Yoon, Hanbin
PY - 2007
Y1 - 2007
N2 - In this paper, we propose a novel FTL (Flash Translation Layer) architecture for NAND flash based applications such as mp3 players, DSCs (Digital still camera) and SSDs (Solid-state disk). Even though the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, its efficient algorithms have a significant impact on performance as well as lifetime. After we categorize dominant parameters that affect performance and endurance, we explore the design space of the FTL architecture based on a diverse workload analysis. With our FTL architectural framework, we can decide which configuration of FTL mapping parameters yields the best performance depending on each NAND flash application behavior.
AB - In this paper, we propose a novel FTL (Flash Translation Layer) architecture for NAND flash based applications such as mp3 players, DSCs (Digital still camera) and SSDs (Solid-state disk). Even though the basic function of an FTL is to translate a logical sector address to a physical sector address in flash memory, its efficient algorithms have a significant impact on performance as well as lifetime. After we categorize dominant parameters that affect performance and endurance, we explore the design space of the FTL architecture based on a diverse workload analysis. With our FTL architectural framework, we can decide which configuration of FTL mapping parameters yields the best performance depending on each NAND flash application behavior.
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U2 - 10.1109/RSP.2007.8
DO - 10.1109/RSP.2007.8
M3 - Conference contribution
AN - SCOPUS:34548724459
SN - 0769528341
SN - 9780769528342
T3 - Proceedings of the International Workshop on Rapid System Prototyping
SP - 202
EP - 208
BT - 18th IEEE/IFIP International Workshop on Rapid System Prototyping, RSP '07, Proceedings
T2 - 18th IEEE/IFIP International Workshop on Rapid System Prototyping, RSP '07
Y2 - 28 May 2007 through 30 May 2007
ER -