This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.
|Title of host publication||Proceedings - 23rd Asian Test Symposium, ATS 2014|
|Publisher||IEEE Computer Society|
|Number of pages||6|
|Publication status||Published - 2014 Dec 7|
|Event||23rd Asian Test Symposium, ATS 2014 - Hangzhou, China|
Duration: 2014 Nov 16 → 2014 Nov 19
|Name||Proceedings of the Asian Test Symposium|
|Other||23rd Asian Test Symposium, ATS 2014|
|Period||14/11/16 → 14/11/19|
Bibliographical notePublisher Copyright:
© 2014 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering