A scalable and parallel test access strategy for NoC-based multicore system

Taewoo Han; Inhyuk Choi; Hyunggoy Oh; Sungho Kang

doi:10.1109/ATS.2014.26

A scalable and parallel test access strategy for NoC-based multicore system

Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

Original language	English
Title of host publication	Proceedings - 23rd Asian Test Symposium, ATS 2014
Publisher	IEEE Computer Society
Pages	81-86
Number of pages	6
ISBN (Electronic)	9781479960309
DOIs	https://doi.org/10.1109/ATS.2014.26
Publication status	Published - 2014 Dec 7
Event	23rd Asian Test Symposium, ATS 2014 - Hangzhou, China Duration: 2014 Nov 16 → 2014 Nov 19

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Other

Other	23rd Asian Test Symposium, ATS 2014
Country/Territory	China
City	Hangzhou
Period	14/11/16 → 14/11/19

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ATS.2014.26

Cite this

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title = "A scalable and parallel test access strategy for NoC-based multicore system",

abstract = "This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.",

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N2 - This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

AB - This paper proposes a new parallel test access strategy for multiple identical cores in a network-on-chip (NoC). The proposed test strategy takes advantage of the regular design of NoC to reduce both test area overhead and test time. The proposed NoC reused test access mechanism (TAM) adopted a pipelining structure and a deterministic test data routing algorithm in order to reuse the full bandwidth of links in the NoC. Also, the architecture has complete scalability according to the number of cores and applications for 3D environment are also represented. Experimental results show that the proposed TAM can test multiple cores with the same test time as a single core and negligible hardware overhead.

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M3 - Conference contribution

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BT - Proceedings - 23rd Asian Test Symposium, ATS 2014

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A scalable and parallel test access strategy for NoC-based multicore system

Abstract

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