A robust enterprise SSD design should provide scalable throughput and storage capacity by integrating (up to thousands) flash chips in a scale-out fashion. However, the current 'channel-based' SSD architecture is not a scalable design choice to allow such a dense integration. Motivated by the inherent architectural scalability of PCIe, we propose UT-SSD, a novel enterprise-scale scale-out SSD architecture, which enables the connection of a large number of (1000s) flash chips using the native PCIe buses instead of the conventional channels. We also propose an architectural enhancement that further improves the performance of our base UT-SSD by maximizing flash utilization. Our experimental analysis of UT-SSD with workloads drawn from various domains shows that the throughput of UT-SSD can reach up to 110 GB/s by successfully aggregating the bandwidth of 4096 flash chips. In addition, our proposed enhancement over this base UT-SSD increases the flash utilization by 50.7%, which in turn results in 116% additional throughput improvement.
|Title of host publication||Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||8|
|Publication status||Published - 2017 Nov 22|
|Event||35th IEEE International Conference on Computer Design, ICCD 2017 - Boston, United States|
Duration: 2017 Nov 5 → 2017 Nov 8
|Name||Proceedings - 35th IEEE International Conference on Computer Design, ICCD 2017|
|Other||35th IEEE International Conference on Computer Design, ICCD 2017|
|Period||17/11/5 → 17/11/8|
Bibliographical notePublisher Copyright:
© 2017 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture