A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages121-122
Number of pages2
ISBN (Electronic)9781538622858
DOIs
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Publication series

NameProceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

Fingerprint

Dynamic random access storage
Silicon
Data acquisition
Scheduling algorithms
Hardware

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Oh, H., Kim, H., Lim, J., & Kang, S. (2018). A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 121-122). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368799
Oh, Hyunggoy ; Kim, Heetae ; Lim, Jaeil ; Kang, Sungho. / A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 121-122 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).
@inproceedings{0dad58011b374ad3b8cfefccbc1a35ab,
title = "A selective error data capture method using on-chip DRAM for silicon debug of multi-core design",
abstract = "In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.",
author = "Hyunggoy Oh and Heetae Kim and Jaeil Lim and Sungho Kang",
year = "2018",
month = "5",
day = "29",
doi = "10.1109/ISOCC.2017.8368799",
language = "English",
series = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "121--122",
booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",
address = "United States",

}

Oh, H, Kim, H, Lim, J & Kang, S 2018, A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 121-122, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368799

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. / Oh, Hyunggoy; Kim, Heetae; Lim, Jaeil; Kang, Sungho.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 121-122 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A selective error data capture method using on-chip DRAM for silicon debug of multi-core design

AU - Oh, Hyunggoy

AU - Kim, Heetae

AU - Lim, Jaeil

AU - Kang, Sungho

PY - 2018/5/29

Y1 - 2018/5/29

N2 - In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.

AB - In multi-core designs, the time overhead for the post-silicon debug is a main challenge because of a large number of cores under debug and the limited resource of design for debug. To overcome this challenge, we propose a selective error data capture method using on-chip DRAM. The key idea is that it is not necessary to capture error-free data of each core. First, the error interval matrix is generated to detect the erroneous intervals of each core by using a multiple-input signature register. And then, the erroneous data capture sequence is used to minimize the number of debug sessions using the debug scheduling algorithm. The experimental results show significant debug time reduction with a negligible hardware overhead compared to the previous work.

UR - http://www.scopus.com/inward/record.url?scp=85048867515&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048867515&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2017.8368799

DO - 10.1109/ISOCC.2017.8368799

M3 - Conference contribution

T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017

SP - 121

EP - 122

BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Oh H, Kim H, Lim J, Kang S. A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. In Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 121-122. (Proceedings - International SoC Design Conference 2017, ISOCC 2017). https://doi.org/10.1109/ISOCC.2017.8368799