We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks with a small two-bank buffer, called a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed, based on two bits in the filter-bank buffer. Energy savings are achieved by reducing the number of entries accessed at a time, by using filtering and the bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. Simulation results show that the energy×delay product can be reduced by about 88% compared with a fully -associative TLB, 75% with respect to a filter-TLB, and 51% relative to a banked-filter TLB.
|Title of host publication||ISLPED 2003 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 2003|
|Event||2003 International Symposium on Low Power Electronics and Design, ISLPED 2003 - Seoul, Korea, Republic of|
Duration: 2003 Aug 25 → 2003 Aug 27
|Name||Proceedings of the International Symposium on Low Power Electronics and Design|
|Conference||2003 International Symposium on Low Power Electronics and Design, ISLPED 2003|
|Country||Korea, Republic of|
|Period||03/8/25 → 03/8/27|
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© 2003 ACM.
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