TY - GEN
T1 - A selectively accessing TLB for high performance and lower power consumption
AU - Min, Jung Hi
AU - Lee, Jung Hoon
AU - Jeong, Seh Woong
AU - Kim, Shin Dug
N1 - Publisher Copyright:
© 2002 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2002
Y1 - 2002
N2 - This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy∗delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy∗Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.
AB - This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy∗delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy∗Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.
UR - http://www.scopus.com/inward/record.url?scp=61349170566&partnerID=8YFLogxK
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U2 - 10.1109/APASIC.2002.1031528
DO - 10.1109/APASIC.2002.1031528
M3 - Conference contribution
AN - SCOPUS:61349170566
T3 - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
SP - 45
EP - 48
BT - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Y2 - 6 August 2002 through 8 August 2002
ER -