A selectively accessing TLB for high performance and lower power consumption

Jung Hi Min; Jung Hoon Lee; Seh Woong Jeong; Shin Dug Kim

doi:10.1109/APASIC.2002.1031528

A selectively accessing TLB for high performance and lower power consumption

Jung Hi Min, Jung Hoon Lee, Seh Woong Jeong, Shin Dug Kim

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy∗delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy∗Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	45-48
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031528
Publication status	Published - 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan, Province of China Duration: 2002 Aug 6 → 2002 Aug 8

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan, Province of China
City	Taipei
Period	02/8/6 → 02/8/8

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/APASIC.2002.1031528

Cite this

Min, J. H., Lee, J. H., Jeong, S. W., & Kim, S. D. (2002). A selectively accessing TLB for high performance and lower power consumption. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 45-48). [1031528] (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031528

@inproceedings{b2e444e60e0b4dcd83a40872f0528648,

title = "A selectively accessing TLB for high performance and lower power consumption",

abstract = "This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy∗delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy∗Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.",

author = "Min, {Jung Hi} and Lee, {Jung Hoon} and Jeong, {Seh Woong} and Kim, {Shin Dug}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 ; Conference date: 06-08-2002 Through 08-08-2002",

year = "2002",

doi = "10.1109/APASIC.2002.1031528",

language = "English",

series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "45--48",

booktitle = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

address = "United States",

}

Min, JH, Lee, JH, Jeong, SW & Kim, SD 2002, A selectively accessing TLB for high performance and lower power consumption. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031528, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 45-48, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, Province of China, 02/8/6. https://doi.org/10.1109/APASIC.2002.1031528

A selectively accessing TLB for high performance and lower power consumption. / Min, Jung Hi; Lee, Jung Hoon; Jeong, Seh Woong; Kim, Shin Dug.

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 45-48 1031528 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A selectively accessing TLB for high performance and lower power consumption

AU - Min, Jung Hi

AU - Lee, Jung Hoon

AU - Jeong, Seh Woong

AU - Kim, Shin Dug

PY - 2002

Y1 - 2002

N2 - This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy∗delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy∗Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.

AB - This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy∗delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy∗Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.

UR - http://www.scopus.com/inward/record.url?scp=61349170566&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=61349170566&partnerID=8YFLogxK

U2 - 10.1109/APASIC.2002.1031528

DO - 10.1109/APASIC.2002.1031528

M3 - Conference contribution

AN - SCOPUS:61349170566

T3 - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

SP - 45

EP - 48

BT - 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002

Y2 - 6 August 2002 through 8 August 2002

ER -

Min JH, Lee JH, Jeong SW, Kim SD. A selectively accessing TLB for high performance and lower power consumption. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2002. p. 45-48. 1031528. (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). https://doi.org/10.1109/APASIC.2002.1031528

A selectively accessing TLB for high performance and lower power consumption

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