A semi-folded instruction format for VLIW architecture

Won Kee Hong; Seung Yup Lee; Shin Dug Kim

doi:10.1109/APASIC.1999.824037

A semi-folded instruction format for VLIW architecture

Won Kee Hong, Seung Yup Lee, Shin Dug Kim

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	95-98
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824037
Publication status	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 1999 Aug 23 → 1999 Aug 25

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Other

Other	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country	Korea, Republic of
City	Seoul
Period	99/8/23 → 99/8/25

Bibliographical note

Publisher Copyright:
© 1999 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials

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title = "A semi-folded instruction format for VLIW architecture",

abstract = "The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.",

author = "Hong, {Won Kee} and Lee, {Seung Yup} and Kim, {Shin Dug}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

year = "1999",

doi = "10.1109/APASIC.1999.824037",

language = "English",

isbn = "0780357051",

series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Hong, WK, Lee, SY & Kim, SD 1999, A semi-folded instruction format for VLIW architecture. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824037, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 95-98, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 99/8/23. https://doi.org/10.1109/APASIC.1999.824037

A semi-folded instruction format for VLIW architecture. / Hong, Won Kee; Lee, Seung Yup; Kim, Shin Dug.

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 95-98 824037 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.

AB - The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.

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A semi-folded instruction format for VLIW architecture

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