@inproceedings{f2200e254ae24ce797c064a32c71e55d,
title = "A semi-folded instruction format for VLIW architecture",
abstract = "The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.",
author = "Hong, {Won Kee} and Lee, {Seung Yup} and Kim, {Shin Dug}",
note = "Publisher Copyright: {\textcopyright} 1999 IEEE. Copyright: Copyright 2018 Elsevier B.V., All rights reserved.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",
year = "1999",
doi = "10.1109/APASIC.1999.824037",
language = "English",
isbn = "0780357051",
series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "95--98",
booktitle = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",
address = "United States",
}