Abstract
The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.
| Original language | English |
|---|---|
| Title of host publication | AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 95-98 |
| Number of pages | 4 |
| ISBN (Print) | 0780357051, 9780780357051 |
| DOIs | |
| Publication status | Published - 1999 |
| Event | 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 1999 Aug 23 → 1999 Aug 25 |
Publication series
| Name | AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs |
|---|
Other
| Other | 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 |
|---|---|
| Country/Territory | Korea, Republic of |
| City | Seoul |
| Period | 99/8/23 → 99/8/25 |
Bibliographical note
Publisher Copyright:© 1999 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Electronic, Optical and Magnetic Materials