A new method of sidelobe level (SLL) reduction for a substrate integrated waveguide (SIW) slot array antenna is presented. In this method, amplitude distribution is assigned to the slots by tapering the SIW width. The SIW with tapered width can be efficiently manufactured by varying the position of the side-wall vias. In this letter, the new method is verified on a 12-element SIW slot array antenna operating at 94 GHz to achieve SLL around -30 dB. The antenna design procedure as well as simulation and measurement results are presented.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering