A Sidelobe Level Reduction Method for mm-Wave Substrate Integrated Waveguide Slot Array Antenna

Aulia Dewantari, Jaeheung Kim, Igor Scherbatko, Min Ho Ka

Research output: Contribution to journalArticle

Abstract

A new method of sidelobe level (SLL) reduction for a substrate integrated waveguide (SIW) slot array antenna is presented. In this method, amplitude distribution is assigned to the slots by tapering the SIW width. The SIW with tapered width can be efficiently manufactured by varying the position of the side-wall vias. In this letter, the new method is verified on a 12-element SIW slot array antenna operating at 94 GHz to achieve SLL around -30 dB. The antenna design procedure as well as simulation and measurement results are presented.

Original languageEnglish
Article number8735804
Pages (from-to)1557-1561
Number of pages5
JournalIEEE Antennas and Wireless Propagation Letters
Volume18
Issue number8
DOIs
Publication statusPublished - 2019 Aug

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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