A small data cache for multimedia-oriented embedded systems

Cheong Ghil Kim, Jung Wook Park, Jung Hoon Lee, Shin-Dug Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively.

Original languageEnglish
Pages (from-to)161-176
Number of pages16
JournalJournal of Systems Architecture
Volume54
Issue number1-2
DOIs
Publication statusPublished - 2008 Jan 1

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Embedded systems
Hardware

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

Kim, Cheong Ghil ; Park, Jung Wook ; Lee, Jung Hoon ; Kim, Shin-Dug. / A small data cache for multimedia-oriented embedded systems. In: Journal of Systems Architecture. 2008 ; Vol. 54, No. 1-2. pp. 161-176.
@article{07f8222c603946859b1dfea8fa4de08b,
title = "A small data cache for multimedia-oriented embedded systems",
abstract = "This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57{\%} and 50{\%} of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively.",
author = "Kim, {Cheong Ghil} and Park, {Jung Wook} and Lee, {Jung Hoon} and Shin-Dug Kim",
year = "2008",
month = "1",
day = "1",
doi = "10.1016/j.sysarc.2007.04.006",
language = "English",
volume = "54",
pages = "161--176",
journal = "Journal of Systems Architecture",
issn = "1383-7621",
publisher = "Elsevier",
number = "1-2",

}

A small data cache for multimedia-oriented embedded systems. / Kim, Cheong Ghil; Park, Jung Wook; Lee, Jung Hoon; Kim, Shin-Dug.

In: Journal of Systems Architecture, Vol. 54, No. 1-2, 01.01.2008, p. 161-176.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A small data cache for multimedia-oriented embedded systems

AU - Kim, Cheong Ghil

AU - Park, Jung Wook

AU - Lee, Jung Hoon

AU - Kim, Shin-Dug

PY - 2008/1/1

Y1 - 2008/1/1

N2 - This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively.

AB - This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively.

UR - http://www.scopus.com/inward/record.url?scp=42749089393&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=42749089393&partnerID=8YFLogxK

U2 - 10.1016/j.sysarc.2007.04.006

DO - 10.1016/j.sysarc.2007.04.006

M3 - Article

VL - 54

SP - 161

EP - 176

JO - Journal of Systems Architecture

JF - Journal of Systems Architecture

SN - 1383-7621

IS - 1-2

ER -