A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-VDD schemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-Times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-VDD scheme, respectively.
|Number of pages||12|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 2022 Apr 1|
Bibliographical notePublisher Copyright:
© 2004-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering