In this work, we investigate the potential of software-only RMT (Redundant MultiThreading) schemes for soft and hard error detection and recovery. We first implement and evaluate the error protection capability of basic software level triple redundant multithreading (STRMT) and analyze its vulnerability. Then we introduce FISHER (FlexIble Soft and Hard Error Resiliency) as a software RMT scheme which can achieve high degree of error resiliency and does not suffer from STRMT vulnerability holes. FISHER executes three threads and rather than having a centralized voting mechanism, it distributes and intertwines error detection and recovery operations between redundant threads. We performed 135,000 soft/hard error injection experiments on different hardware components of an ARM cortex53-like μ-architecturally simulated microprocessor. The results demonstrate that FISHER can reduce programs failure rate by around 42× and 26× compared to original and basic STRMT-protected versions of programs, respectively.
|Title of host publication||Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2019 May 14|
|Event||22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 - Florence, Italy|
Duration: 2019 Mar 25 → 2019 Mar 29
|Name||Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019|
|Conference||22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019|
|Period||19/3/25 → 19/3/29|
Bibliographical noteFunding Information:
VI. ACKNOWLEDGEMENTS This work was partially supported by funding from NS-FCCF 1055094 (CAREER); by funding from NRF-2016H1A2A1909470 (Global PH.D. Fellowship Program, NRF, the Ministry of Education); by funding from NRF-2015M3C4A7065522 (Next-generation Information Computing Development Program, NRF, MSIT); by funding from 2014-3-00035 (High Performance and Scalable Manycore Operating System, IITP, MSIT).
© 2019 EDAA.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Control and Optimization