A spur free 0.4-V 88-μW 200-MHz phase-locked loop

Joung Wook Moon, Kwang Chun Choi, Min Hyeong Kim, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages134-137
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Moon, J. W., Choi, K. C., Kim, M. H., & Choi, W. Y. (2013). A spur free 0.4-V 88-μW 200-MHz phase-locked loop. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 134-137). [6864005] (ISOCC 2013 - 2013 International SoC Design Conference). IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6864005