A spur free 0.4-V 88-μW 200-MHz phase-locked loop

Joung Wook Moon, Kwang Chun Choi, Min Hyeong Kim, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages134-137
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

Fingerprint

Phase locked loops
Charge pump circuits
Variable frequency oscillators
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Moon, J. W., Choi, K. C., Kim, M. H., & Choi, W. Y. (2013). A spur free 0.4-V 88-μW 200-MHz phase-locked loop. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 134-137). [6864005] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6864005
Moon, Joung Wook ; Choi, Kwang Chun ; Kim, Min Hyeong ; Choi, Woo Young. / A spur free 0.4-V 88-μW 200-MHz phase-locked loop. ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. pp. 134-137
@inproceedings{be531e0385ad49f1b0ed796b397f733f,
title = "A spur free 0.4-V 88-μW 200-MHz phase-locked loop",
abstract = "An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.",
author = "Moon, {Joung Wook} and Choi, {Kwang Chun} and Kim, {Min Hyeong} and Choi, {Woo Young}",
year = "2013",
month = "1",
day = "1",
doi = "10.1109/ISOCC.2013.6864005",
language = "English",
isbn = "9781479911417",
pages = "134--137",
booktitle = "ISOCC 2013 - 2013 International SoC Design Conference",
publisher = "IEEE Computer Society",
address = "United States",

}

Moon, JW, Choi, KC, Kim, MH & Choi, WY 2013, A spur free 0.4-V 88-μW 200-MHz phase-locked loop. in ISOCC 2013 - 2013 International SoC Design Conference., 6864005, IEEE Computer Society, pp. 134-137, 2013 International SoC Design Conference, ISOCC 2013, Busan, Korea, Republic of, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6864005

A spur free 0.4-V 88-μW 200-MHz phase-locked loop. / Moon, Joung Wook; Choi, Kwang Chun; Kim, Min Hyeong; Choi, Woo Young.

ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 134-137 6864005.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A spur free 0.4-V 88-μW 200-MHz phase-locked loop

AU - Moon, Joung Wook

AU - Choi, Kwang Chun

AU - Kim, Min Hyeong

AU - Choi, Woo Young

PY - 2013/1/1

Y1 - 2013/1/1

N2 - An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

AB - An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm2 and consumes 88 μW at 0.4-V supply for 200-MHz operation.

UR - http://www.scopus.com/inward/record.url?scp=84906896241&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84906896241&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2013.6864005

DO - 10.1109/ISOCC.2013.6864005

M3 - Conference contribution

SN - 9781479911417

SP - 134

EP - 137

BT - ISOCC 2013 - 2013 International SoC Design Conference

PB - IEEE Computer Society

ER -

Moon JW, Choi KC, Kim MH, Choi WY. A spur free 0.4-V 88-μW 200-MHz phase-locked loop. In ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society. 2013. p. 134-137. 6864005 https://doi.org/10.1109/ISOCC.2013.6864005