Abstract
Current rapid advancements in deep submicron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. Spare architectures for the repair of faulty memory include one-dimensional (1D) spare architectures, two-dimensional (2D) spare architectures, and configurable spare architectures. Of these types, 2D spare architectures, which prepare extra rows and columns for repair, are popular because of their better repairing efficiency than 1D spare architectures and easier implementation than configurable spare architectures. However, because the complexity of the RA is NP-complete, the RA algorithm should consider various factors in order to determine a repair solution. The performance depends on three factors: Analysis time, repair rate, and area overhead. In this article, we survey RA algorithms for memory devices as well as built-in repair algorithms for improving these performance factors. Builtin redundancy analysis techniques for emergent three-dimensional integrated circuits are also discussed. Based on this analysis, we then discuss future research challenges for faulty-memory repair studies.
| Original language | English |
|---|---|
| Article number | 47 |
| Journal | ACM Computing Surveys |
| Volume | 49 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2016 Oct 1 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)
Cite this
}
A survey of repair analysis algorithms for memories. / Cho, Keewon; Kang, Wooheon; Cho, Hyungjun; Lee, Changwook; Kang, Sungho.
In: ACM Computing Surveys, Vol. 49, No. 3, 47, 01.10.2016.Research output: Contribution to journal › Article
TY - JOUR
T1 - A survey of repair analysis algorithms for memories
AU - Cho, Keewon
AU - Kang, Wooheon
AU - Cho, Hyungjun
AU - Lee, Changwook
AU - Kang, Sungho
PY - 2016/10/1
Y1 - 2016/10/1
N2 - Current rapid advancements in deep submicron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. Spare architectures for the repair of faulty memory include one-dimensional (1D) spare architectures, two-dimensional (2D) spare architectures, and configurable spare architectures. Of these types, 2D spare architectures, which prepare extra rows and columns for repair, are popular because of their better repairing efficiency than 1D spare architectures and easier implementation than configurable spare architectures. However, because the complexity of the RA is NP-complete, the RA algorithm should consider various factors in order to determine a repair solution. The performance depends on three factors: Analysis time, repair rate, and area overhead. In this article, we survey RA algorithms for memory devices as well as built-in repair algorithms for improving these performance factors. Builtin redundancy analysis techniques for emergent three-dimensional integrated circuits are also discussed. Based on this analysis, we then discuss future research challenges for faulty-memory repair studies.
AB - Current rapid advancements in deep submicron technologies have enabled the implementation of very large memory devices and embedded memories. However, the memory growth increases the number of defects, reducing the yield and reliability of such devices. Faulty cells are commonly repaired by using redundant cells, which are embedded in memory arrays by adding spare rows and columns. The repair process requires an efficient redundancy analysis (RA) algorithm. Spare architectures for the repair of faulty memory include one-dimensional (1D) spare architectures, two-dimensional (2D) spare architectures, and configurable spare architectures. Of these types, 2D spare architectures, which prepare extra rows and columns for repair, are popular because of their better repairing efficiency than 1D spare architectures and easier implementation than configurable spare architectures. However, because the complexity of the RA is NP-complete, the RA algorithm should consider various factors in order to determine a repair solution. The performance depends on three factors: Analysis time, repair rate, and area overhead. In this article, we survey RA algorithms for memory devices as well as built-in repair algorithms for improving these performance factors. Builtin redundancy analysis techniques for emergent three-dimensional integrated circuits are also discussed. Based on this analysis, we then discuss future research challenges for faulty-memory repair studies.
UR - http://www.scopus.com/inward/record.url?scp=84993995170&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84993995170&partnerID=8YFLogxK
U2 - 10.1145/2971481
DO - 10.1145/2971481
M3 - Article
VL - 49
JO - ACM Computing Surveys
JF - ACM Computing Surveys
SN - 0360-0300
IS - 3
M1 - 47
ER -