A time-interleaved switched-capacitor band-pass delta-sigma modulator

Minho Kwon, Jungyoon Lee, Gunhee Han

Research output: Contribution to journalConference article

Abstract

A band-pass delta-sigma modulator (BPDSM) is a key building block of a digital intermediate frequency (IF) of a wireless communication. A BPDSM is difficult to implement with switched-capacitor (SC) circuits at high IF frequencies due to the high, clock rate requirement. This paper proposes a time-interleaved (TI) SC BPDSM architecture that can operate in higher frequency than the conventional BPDSM architecture. The proposed 5-stage TI architecture with recursive feedback loop provides a reduction in the clock frequency requirement by a factor of 5 and relieves the settling time requirement to one-fourth of what the same period. The test chip was designed and fabricated for a 30 MHz IF system with a 0.35-nm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW and occupying 1.3 mm2.

Original languageEnglish
Pages (from-to)I941-I944
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 2003 Jul 14
EventProceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 2003 May 252003 May 28

Fingerprint

Modulators
Capacitors
Clocks
Feedback
Bandwidth
Networks (circuits)
Communication

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "A band-pass delta-sigma modulator (BPDSM) is a key building block of a digital intermediate frequency (IF) of a wireless communication. A BPDSM is difficult to implement with switched-capacitor (SC) circuits at high IF frequencies due to the high, clock rate requirement. This paper proposes a time-interleaved (TI) SC BPDSM architecture that can operate in higher frequency than the conventional BPDSM architecture. The proposed 5-stage TI architecture with recursive feedback loop provides a reduction in the clock frequency requirement by a factor of 5 and relieves the settling time requirement to one-fourth of what the same period. The test chip was designed and fabricated for a 30 MHz IF system with a 0.35-nm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW and occupying 1.3 mm2.",
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A time-interleaved switched-capacitor band-pass delta-sigma modulator. / Kwon, Minho; Lee, Jungyoon; Han, Gunhee.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 1, 14.07.2003, p. I941-I944.

Research output: Contribution to journalConference article

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