Abstract
A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.
| Original language | English |
|---|---|
| Pages (from-to) | 785-790 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Electronics |
| Volume | E87-C |
| Issue number | 5 |
| Publication status | Published - 2004 May |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Cite this
Kwon, M., Lee, J., & Han, G. (2004). A time-interleaved switched-capacitor band-pass delta-sigma modulator with recursive loop. IEICE Transactions on Electronics, E87-C(5), 785-790.