A time-interleaved switched-capacitor band-pass delta-sigma modulator with recursive loop

Minho Kwon, Jungyoon Lee, Gunhee Han

Research output: Contribution to journalArticle

Abstract

A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

Original languageEnglish
Pages (from-to)785-790
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE87-C
Issue number5
Publication statusPublished - 2004 Jan 1

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Modulators
Capacitors
Clocks
Communication systems
Bandwidth

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

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A time-interleaved switched-capacitor band-pass delta-sigma modulator with recursive loop. / Kwon, Minho; Lee, Jungyoon; Han, Gunhee.

In: IEICE Transactions on Electronics, Vol. E87-C, No. 5, 01.01.2004, p. 785-790.

Research output: Contribution to journalArticle

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