A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm 2 chip area.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2012 Mar|
Bibliographical noteFunding Information:
Manuscript received July 4, 2011; revised September 26, 2011 and November 23, 2011; accepted December 18, 2011. Date of publication February 3, 2012; date of current version March 16, 2012. This work was supported by the IT R&D program of MKE/KEIT [KI002197, Development of Scalable Micro Flow Processing Technology]. This paper was recommended by Associate Editor S. Naraghi.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering