A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector

Kwang Chun Choi; Seung Woo Lee; Bhum Cheol Lee; Woo Young Choi

doi:10.1109/TCSII.2012.2184370

A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector

Kwang Chun Choi, Seung Woo Lee, Bhum Cheol Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

22 Citations (Scopus)

Abstract

A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm ² chip area.

Original language	English
Article number	6145624
Pages (from-to)	143-147
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	59
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2012.2184370
Publication status	Published - 2012 Mar

Bibliographical note

Funding Information:
Manuscript received July 4, 2011; revised September 26, 2011 and November 23, 2011; accepted December 18, 2011. Date of publication February 3, 2012; date of current version March 16, 2012. This work was supported by the IT R&D program of MKE/KEIT [KI002197, Development of Scalable Micro Flow Processing Technology]. This paper was recommended by Associate Editor S. Naraghi.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2012.2184370

Cite this

@article{b7f99fad919d42ac9647a927fd54f281,

title = "A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector",

abstract = "A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm 2 chip area.",

author = "Choi, {Kwang Chun} and Lee, {Seung Woo} and Lee, {Bhum Cheol} and Choi, {Woo Young}",

note = "Funding Information: Manuscript received July 4, 2011; revised September 26, 2011 and November 23, 2011; accepted December 18, 2011. Date of publication February 3, 2012; date of current version March 16, 2012. This work was supported by the IT R&D program of MKE/KEIT [KI002197, Development of Scalable Micro Flow Processing Technology]. This paper was recommended by Associate Editor S. Naraghi.",

year = "2012",

month = mar,

doi = "10.1109/TCSII.2012.2184370",

language = "English",

volume = "59",

pages = "143--147",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector

AU - Choi, Kwang Chun

AU - Lee, Seung Woo

AU - Lee, Bhum Cheol

AU - Choi, Woo Young

N1 - Funding Information: Manuscript received July 4, 2011; revised September 26, 2011 and November 23, 2011; accepted December 18, 2011. Date of publication February 3, 2012; date of current version March 16, 2012. This work was supported by the IT R&D program of MKE/KEIT [KI002197, Development of Scalable Micro Flow Processing Technology]. This paper was recommended by Associate Editor S. Naraghi.

PY - 2012/3

Y1 - 2012/3

N2 - A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm 2 chip area.

AB - A new type of sampling error corrector for a time-to-digital converter (TDC) having a multiphase reference clock and a binary counter is demonstrated. With this corrector, sampling errors caused by asynchronous TDC inputs are corrected without requiring additional counters or reclocking circuits. A TDC having the corrector is implemented in 90-nm CMOS logic technology. It has 13.6-ps/least significant bit resolution and 13-bit input dynamic range. It consumes 18 mW from a 1.2-V supply and occupies a 100 × 210 μm 2 chip area.

UR - http://www.scopus.com/inward/record.url?scp=84858953816&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84858953816&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2012.2184370

DO - 10.1109/TCSII.2012.2184370

M3 - Article

AN - SCOPUS:84858953816

SN - 1549-7747

VL - 59

SP - 143

EP - 147

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

M1 - 6145624

ER -

A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector

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Bibliographical note

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