A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs

Young Woo Lee, Junghwan Kim, Inhyuk Choi, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

After the 3D stacking process, TSV-based 3D-ICs are required to perform the post-bond testing in order to detect TSV faults or device functional defects. To detect the resistive open and bridge defects, various effective TSV testing techniques have been studied. At an early stage of TSV manufacturing, it is important to consider that the TSV testing is required not only determining whether each TSV is defective or non-defective, but also digitizing the fault degree into the TSV resistance value during the silicon debugging. In this paper, we propose a new TSV test structure for simultaneously detecting the resistive open and bridge defects with supporting the debug mode to analysis the characteristic of the specific TSV. It can highly reduce the test time by detecting TSV defects at the same time without compromising test quality.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages129-130
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Other

Other13th International SoC Design Conference, ISOCC 2016
CountryKorea, Republic of
CityJeju
Period16/10/2316/10/26

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Defects
defects
Testing
checkout
Silicon
manufacturing
silicon

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Lee, Y. W., Kim, J., Choi, I., & Kang, S. (2016). A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 129-130). [7799724] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799724
Lee, Young Woo ; Kim, Junghwan ; Choi, Inhyuk ; Kang, Sungho. / A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 129-130
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abstract = "After the 3D stacking process, TSV-based 3D-ICs are required to perform the post-bond testing in order to detect TSV faults or device functional defects. To detect the resistive open and bridge defects, various effective TSV testing techniques have been studied. At an early stage of TSV manufacturing, it is important to consider that the TSV testing is required not only determining whether each TSV is defective or non-defective, but also digitizing the fault degree into the TSV resistance value during the silicon debugging. In this paper, we propose a new TSV test structure for simultaneously detecting the resistive open and bridge defects with supporting the debug mode to analysis the characteristic of the specific TSV. It can highly reduce the test time by detecting TSV defects at the same time without compromising test quality.",
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Lee, YW, Kim, J, Choi, I & Kang, S 2016, A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799724, Institute of Electrical and Electronics Engineers Inc., pp. 129-130, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799724

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. / Lee, Young Woo; Kim, Junghwan; Choi, Inhyuk; Kang, Sungho.

ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 129-130 7799724.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lee YW, Kim J, Choi I, Kang S. A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc. 2016. p. 129-130. 7799724 https://doi.org/10.1109/ISOCC.2016.7799724