A way enabling mechanism based on the branch prediction information for low power instruction cache

Gi Ho Park, Jung Wook Park, Hoi Jin Lee, Gunok Jung, Sung Bae Park, Shin-Dug Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a cache way enabling mechanism using branch target addresses. This mechanism uses branch prediction information to avoid the power consumption due to unnecessary cache way access by enabling only the cache way(s) that should be accessed. The proposed cache way enabling mechanism reduces the power consumption of the instruction cache by 63% without any performance degradation of the processor. An ARM1136 processor simulator and the Synopsys PrimeTime are used to perform the performance/power simulation and static timing analysis of the proposed mechanisms respectively.

Original languageEnglish
Pages (from-to)517-521
Number of pages5
JournalIEICE Transactions on Electronics
VolumeE92-C
Issue number4
DOIs
Publication statusPublished - 2009 Jan 1

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Electric power utilization
Simulators
Degradation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Park, Gi Ho ; Park, Jung Wook ; Lee, Hoi Jin ; Jung, Gunok ; Park, Sung Bae ; Kim, Shin-Dug. / A way enabling mechanism based on the branch prediction information for low power instruction cache. In: IEICE Transactions on Electronics. 2009 ; Vol. E92-C, No. 4. pp. 517-521.
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A way enabling mechanism based on the branch prediction information for low power instruction cache. / Park, Gi Ho; Park, Jung Wook; Lee, Hoi Jin; Jung, Gunok; Park, Sung Bae; Kim, Shin-Dug.

In: IEICE Transactions on Electronics, Vol. E92-C, No. 4, 01.01.2009, p. 517-521.

Research output: Contribution to journalArticle

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