Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology

T. H. Choi; H. W. Choi; J. H. Choi; H. T. Choo; H. C. Jung; H. Y. Kim; T. J. Song; J. O. Kye; S. O. Jung

doi:10.23919/VLSIT.2019.8776509

Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology

T. H. Choi, H. W. Choi, J. H. Choi, H. T. Choo, H. C. Jung, H. Y. Kim, T. J. Song, J. O. Kye, S. O. Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (I_ds) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian I_ds distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (R_ch-f) and source/drain external resistance (R_ext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.

Original language	English
Title of host publication	2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T106-T107
ISBN (Electronic)	9784863487178
DOIs	https://doi.org/10.23919/VLSIT.2019.8776509
Publication status	Published - 2019 Jun
Event	39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan Duration: 2019 Jun 9 → 2019 Jun 14

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2019-June
ISSN (Print)	0743-1562

Conference

Conference	39th Symposium on VLSI Technology, VLSI Technology 2019
Country	Japan
City	Kyoto
Period	19/6/9 → 19/6/14

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.23919/VLSIT.2019.8776509

Fingerprint Dive into the research topics of 'Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology'. Together they form a unique fingerprint.

Cite this

Choi, T. H., Choi, H. W., Choi, J. H., Choo, H. T., Jung, H. C., Kim, H. Y., Song, T. J., Kye, J. O., & Jung, S. O. (2019). Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T106-T107). [8776509] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776509

Choi, T. H. ; Choi, H. W. ; Choi, J. H. ; Choo, H. T. ; Jung, H. C. ; Kim, H. Y. ; Song, T. J. ; Kye, J. O. ; Jung, S. O. / Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology. 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. pp. T106-T107 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{5f3826b0dcf1493fa79ee056e8bcbc8c,

title = "Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology",

abstract = "High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (Ids) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian Ids distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (Rch-f) and source/drain external resistance (Rext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.",

author = "Choi, {T. H.} and Choi, {H. W.} and Choi, {J. H.} and Choo, {H. T.} and Jung, {H. C.} and Kim, {H. Y.} and Song, {T. J.} and Kye, {J. O.} and Jung, {S. O.}",

year = "2019",

month = jun,

doi = "10.23919/VLSIT.2019.8776509",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "T106--T107",

booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",

address = "United States",

note = "39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

}

Choi, TH, Choi, HW, Choi, JH, Choo, HT, Jung, HC, Kim, HY, Song, TJ, Kye, JO & Jung, SO 2019, Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776509, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T106-T107, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 19/6/9. https://doi.org/10.23919/VLSIT.2019.8776509

Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology. / Choi, T. H.; Choi, H. W.; Choi, J. H.; Choo, H. T.; Jung, H. C.; Kim, H. Y.; Song, T. J.; Kye, J. O.; Jung, S. O.

2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. T106-T107 8776509 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology

AU - Choi, T. H.

AU - Choi, H. W.

AU - Choi, J. H.

AU - Choo, H. T.

AU - Jung, H. C.

AU - Kim, H. Y.

AU - Song, T. J.

AU - Kye, J. O.

AU - Jung, S. O.

PY - 2019/6

Y1 - 2019/6

N2 - High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (Ids) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian Ids distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (Rch-f) and source/drain external resistance (Rext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.

AB - High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (Ids) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian Ids distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (Rch-f) and source/drain external resistance (Rext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.

UR - http://www.scopus.com/inward/record.url?scp=85070285530&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85070285530&partnerID=8YFLogxK

U2 - 10.23919/VLSIT.2019.8776509

DO - 10.23919/VLSIT.2019.8776509

M3 - Conference contribution

AN - SCOPUS:85070285530

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T106-T107

BT - 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 39th Symposium on VLSI Technology, VLSI Technology 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

Choi TH, Choi HW, Choi JH, Choo HT, Jung HC, Kim HY et al. Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. T106-T107. 8776509. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.23919/VLSIT.2019.8776509