Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology

T. H. Choi, H. W. Choi, J. H. Choi, H. T. Choo, H. C. Jung, H. Y. Kim, T. J. Song, J. O. Kye, S. O. Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (Ids) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian Ids distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (Rch-f) and source/drain external resistance (Rext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.

Original languageEnglish
Title of host publication2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesT106-T107
ISBN (Electronic)9784863487178
DOIs
Publication statusPublished - 2019 Jun
Event39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan
Duration: 2019 Jun 92019 Jun 14

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2019-June
ISSN (Print)0743-1562

Conference

Conference39th Symposium on VLSI Technology, VLSI Technology 2019
CountryJapan
CityKyoto
Period19/6/919/6/14

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Choi, T. H., Choi, H. W., Choi, J. H., Choo, H. T., Jung, H. C., Kim, H. Y., Song, T. J., Kye, J. O., & Jung, S. O. (2019). Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T106-T107). [8776509] (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776509