@inproceedings{5f3826b0dcf1493fa79ee056e8bcbc8c,
title = "Accurate High-Sigma Mismatch Model for Low Power Design in Sub-7nm Technology",
abstract = "High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (Ids) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian Ids distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (Rch-f) and source/drain external resistance (Rext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.",
author = "Choi, {T. H.} and Choi, {H. W.} and Choi, {J. H.} and Choo, {H. T.} and Jung, {H. C.} and Kim, {H. Y.} and Song, {T. J.} and Kye, {J. O.} and Jung, {S. O.}",
note = "Publisher Copyright: {\textcopyright} 2019 The Japan Society of Applied Physics. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.; 39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",
year = "2019",
month = jun,
doi = "10.23919/VLSIT.2019.8776509",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T106--T107",
booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",
address = "United States",
}