High-sigma yield simulation analysis based on accurate SPICE mismatch model is required for high volume product design. Especially for the low power design in sub-7nm technology, the non-Gaussian behavior of the transistor drain currents (Ids) is intensifying due to large mismatch variation. To achieve reliable high-sigma simulation, SPICE mismatch model needs to accurately reflect the non-Gaussian Ids distribution obtained from the silicon data. Gaussian distribution modeling of channel resistance factor (Rch-f) and source/drain external resistance (Rext) is proven to be effective to model the skewed Gaussian distribution shape of massive silicon Ids data.
|Title of host publication||2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Jun|
|Event||39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan|
Duration: 2019 Jun 9 → 2019 Jun 14
|Name||Digest of Technical Papers - Symposium on VLSI Technology|
|Conference||39th Symposium on VLSI Technology, VLSI Technology 2019|
|Period||19/6/9 → 19/6/14|
Bibliographical notePublisher Copyright:
© 2019 The Japan Society of Applied Physics.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering