A/D converter using iterative divide-by-two reference for CMOS image sensor

Lee Jeonghwan, Han Gunhee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes an ADC using Iterative Divide-by-Two Reference. Using and sharing a single voltage divider reduces silicon area for a column compared with the conventional SA-ADC. An offset-cancelled integrator and a capacitor error averaging method are implemented to decrease the impact of nonlinearities. The ADC is designed in 0.18-μm CMOS process and consumes 0.35-mW of power per ADC, and the active die area is 0.012-mm2.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
Volume3
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 2008 Nov 242008 Nov 25

Other

Other2008 International SoC Design Conference, ISOCC 2008
CountryKorea, Republic of
CityBusan
Period08/11/2408/11/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

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    Jeonghwan, L., & Gunhee, H. (2008). A/D converter using iterative divide-by-two reference for CMOS image sensor. In 2008 International SoC Design Conference, ISOCC 2008 (Vol. 3). [4815737] https://doi.org/10.1109/SOCDC.2008.4815737