Abstract
This paper proposes an ADC using Iterative Divide-by-Two Reference. Using and sharing a single voltage divider reduces silicon area for a column compared with the conventional SA-ADC. An offset-cancelled integrator and a capacitor error averaging method are implemented to decrease the impact of nonlinearities. The ADC is designed in 0.18-μm CMOS process and consumes 0.35-mW of power per ADC, and the active die area is 0.012-mm2.
| Original language | English |
|---|---|
| Title of host publication | 2008 International SoC Design Conference, ISOCC 2008 |
| Volume | 3 |
| DOIs | |
| Publication status | Published - 2008 Dec 1 |
| Event | 2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of Duration: 2008 Nov 24 → 2008 Nov 25 |
Other
| Other | 2008 International SoC Design Conference, ISOCC 2008 |
|---|---|
| Country | Korea, Republic of |
| City | Busan |
| Period | 08/11/24 → 08/11/25 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Software
Cite this
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A/D converter using iterative divide-by-two reference for CMOS image sensor. / Jeonghwan, Lee; Gunhee, Han.
2008 International SoC Design Conference, ISOCC 2008. Vol. 3 2008. 4815737.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A/D converter using iterative divide-by-two reference for CMOS image sensor
AU - Jeonghwan, Lee
AU - Gunhee, Han
PY - 2008/12/1
Y1 - 2008/12/1
N2 - This paper proposes an ADC using Iterative Divide-by-Two Reference. Using and sharing a single voltage divider reduces silicon area for a column compared with the conventional SA-ADC. An offset-cancelled integrator and a capacitor error averaging method are implemented to decrease the impact of nonlinearities. The ADC is designed in 0.18-μm CMOS process and consumes 0.35-mW of power per ADC, and the active die area is 0.012-mm2.
AB - This paper proposes an ADC using Iterative Divide-by-Two Reference. Using and sharing a single voltage divider reduces silicon area for a column compared with the conventional SA-ADC. An offset-cancelled integrator and a capacitor error averaging method are implemented to decrease the impact of nonlinearities. The ADC is designed in 0.18-μm CMOS process and consumes 0.35-mW of power per ADC, and the active die area is 0.012-mm2.
UR - http://www.scopus.com/inward/record.url?scp=67650659393&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67650659393&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2008.4815737
DO - 10.1109/SOCDC.2008.4815737
M3 - Conference contribution
AN - SCOPUS:67650659393
SN - 9781424425990
SN - 9781424425990
VL - 3
BT - 2008 International SoC Design Conference, ISOCC 2008
ER -