The optimization of cells and cell combinations used in design is critical to enhance the performance. If frequently used cell combinations are known in advance, a new cell development can be significantly optimized using the cell combinations for chip design. However, extracting frequent cell combinations is an NP hard problem. We propose a new framework, referring as AFSEM, to extract frequent cell combinations for design optimization. To solve this problem, we use a frequent subgraph mining method which is a process of discovering subgraphs. We present an advanced graph modeling and optimized frequent subgraph mining platform for a practical use. The experimental results with various designs demonstrate that the proposed method can discover various types of subcircuits for design optimization with various runtime optimization methods.
|Title of host publication||ISCAS 2016 - IEEE International Symposium on Circuits and Systems|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|Publication status||Published - 2016 Jul 29|
|Event||2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada|
Duration: 2016 May 22 → 2016 May 25
|Name||Proceedings - IEEE International Symposium on Circuits and Systems|
|Other||2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016|
|Period||16/5/22 → 16/5/25|
Bibliographical notePublisher Copyright:
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering