This paper proposes a 90° phase-shift delay-locked loop (DLL) used in dynamic RAM for data sampling clock generation. The proposed DLL alleviates process variation issues, which are mainly caused by the mismatch between the delay line segments in the previous 90° phase-shift DLLs, and reduces area by adopting a multiplying DLL-based structure. In addition, a novel jitter suppression scheme is also proposed to suppress control code dithering. A stochastic analysis is performed to evaluate the effectiveness of the proposed dithering jitter suppression. The proposed DLL is fabricated using a 45-nm CMOS process on an active area of 69.9 μm × 49.3 μm and utilizes a 1.1 V supply voltage. The proposed DLL has an operating frequency ranging from 500 to 800 MHz and consumes 1.32 mW at 800 MHz. The measured rms and peak-to-peak output jitters are improved by 5.42% to 18.75% and 5.52% to 18.31%, respectively, in the entire operating frequency range.
|Number of pages||10|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2016 Mar|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering