All-digital 90°phase-shift DLL with a dithering jitter suppression scheme

Dong Hoon Jung, Kyungho Ryu, Jung Hyun Park, Won Lee, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467361460
DOIs
Publication statusPublished - 2013 Nov 7
Event35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
Duration: 2013 Sep 222013 Sep 25

Other

Other35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
CountryUnited States
CitySan Jose, CA
Period13/9/2213/9/25

Fingerprint

Jitter
Electric delay lines
Clocks
Electric power utilization
Electric potential

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Jung, D. H., Ryu, K., Park, J. H., Lee, W., & Jung, S. O. (2013). All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 [6658534] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658534
Jung, Dong Hoon ; Ryu, Kyungho ; Park, Jung Hyun ; Lee, Won ; Jung, Seong Ook. / All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013.
@inproceedings{e56d58e20c6b48b0832a7e110ce48bc5,
title = "All-digital 90°phase-shift DLL with a dithering jitter suppression scheme",
abstract = "We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.",
author = "Jung, {Dong Hoon} and Kyungho Ryu and Park, {Jung Hyun} and Won Lee and Jung, {Seong Ook}",
year = "2013",
month = "11",
day = "7",
doi = "10.1109/CICC.2013.6658534",
language = "English",
isbn = "9781467361460",
booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

Jung, DH, Ryu, K, Park, JH, Lee, W & Jung, SO 2013, All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. in Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013., 6658534, Institute of Electrical and Electronics Engineers Inc., 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, United States, 13/9/22. https://doi.org/10.1109/CICC.2013.6658534

All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. / Jung, Dong Hoon; Ryu, Kyungho; Park, Jung Hyun; Lee, Won; Jung, Seong Ook.

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. 6658534.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - All-digital 90°phase-shift DLL with a dithering jitter suppression scheme

AU - Jung, Dong Hoon

AU - Ryu, Kyungho

AU - Park, Jung Hyun

AU - Lee, Won

AU - Jung, Seong Ook

PY - 2013/11/7

Y1 - 2013/11/7

N2 - We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.

AB - We propose a 90°phase-shift digital delay-locked loop (DLL) with a new dithering jitter suppression scheme. Delay-line control code dithering is effectively suppressed by comparing the distribution of the input and the output clock jitter. The proposed scheme is analyzed through a stochastic calculation. A test chip is fabricated using a 45-nm CMOS technology, and a 1.95-ps rms and 12.89-ps peak-to-peak jitter are achieved at 800-MHz operating frequency with a 1.1-V supply voltage. The measured power consumption is 1.32 mW at 800 MHz, and the active chip area is 69.9 /am χ 49.3 /am.

UR - http://www.scopus.com/inward/record.url?scp=84892655315&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84892655315&partnerID=8YFLogxK

U2 - 10.1109/CICC.2013.6658534

DO - 10.1109/CICC.2013.6658534

M3 - Conference contribution

SN - 9781467361460

BT - Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Jung DH, Ryu K, Park JH, Lee W, Jung SO. All-digital 90°phase-shift DLL with a dithering jitter suppression scheme. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc. 2013. 6658534 https://doi.org/10.1109/CICC.2013.6658534