A fast-locking all-digital delay-locked loop (DLL) with closed-loop duty-cycle correction (DCC) capability is proposed for clock synchronization in DRAM. A new cyclic-locking loop is proposed to resolve the locking speed degradation due to the replica delay line (RDL) in the DLL. The proposed cyclic-locking loop operates asynchronously and offers an optimal loop delay for DLL locking. The locking time of the proposed DLL is decreased by more than 34.1% compared to that of previous fast-locking DLLs using a successive approximation register algorithm. The proposed DLL is fabricated using 65-nm CMOS process technology on an active area of 465.1× 37μ m2 and uses a 1.1-V supply voltage. The operating frequency range is 400-800 MHz, and 3.52 mW is consumed at 800 MHz, resulting in a power consumption of 4.4 pJ/Hz. The measured locking time ranges from 38 to 41 cycles over the entire operating frequency range.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2015 Nov 1|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering