All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate

Kyungho Ryu, Dong Hoon Jung, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.

Original languageEnglish
Title of host publicationESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference
Pages41-44
Number of pages4
DOIs
Publication statusPublished - 2013 Dec 31
Event39th European Solid-State Circuits Conference, ESSCIRC 2013 - Bucharest
Duration: 2013 Sep 162013 Sep 20

Other

Other39th European Solid-State Circuits Conference, ESSCIRC 2013
CityBucharest
Period13/9/1613/9/20

Fingerprint

Automatic testing
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ryu, K., Jung, D. H., & Jung, S. O. (2013). All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. In ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference (pp. 41-44). [6649067] https://doi.org/10.1109/ESSCIRC.2013.6649067
Ryu, Kyungho ; Jung, Dong Hoon ; Jung, Seong Ook. / All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference. 2013. pp. 41-44
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abstract = "We propose a timing generator for use in high-performance automatic testing equipment that achieves a high, wide-range test cycle frequency and process variation tolerance using four sub-timing generators and a CLKRATE divider. Each sub-timing generator is composed of an edge vernier, an integer delay generator, and an offset canceller. A prototype chip fabricated using 0.13-μm CMOS technology can achieve an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.",
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Ryu, K, Jung, DH & Jung, SO 2013, All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. in ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference., 6649067, pp. 41-44, 39th European Solid-State Circuits Conference, ESSCIRC 2013, Bucharest, 13/9/16. https://doi.org/10.1109/ESSCIRC.2013.6649067

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. / Ryu, Kyungho; Jung, Dong Hoon; Jung, Seong Ook.

ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference. 2013. p. 41-44 6649067.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Ryu K, Jung DH, Jung SO. All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. In ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference. 2013. p. 41-44. 6649067 https://doi.org/10.1109/ESSCIRC.2013.6649067