Abstract
In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators operating in parallel. In addition, to improve process variation robustness, a precise eight-phase generator consisting of an accurate reference generator and a phase generator with dual-loop calibration (CAL) is proposed, and a phase error of less than 1.21° is achieved. Dynamic and static CAL techniques are also adopted in the edge vernier. A prototype chip having eight channels is fabricated using 0.13-μm CMOS technology. The proposed timing generator has an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.
| Original language | English |
|---|---|
| Pages (from-to) | 1015-1025 |
| Number of pages | 11 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 26 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 2018 Jun 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
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All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate. / Jung, Dong Hoon; Ryu, Kyungho; Park, Jung Hyun; Jung, Seongook.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 6, 01.06.2018, p. 1015-1025.Research output: Contribution to journal › Article
TY - JOUR
T1 - All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate
AU - Jung, Dong Hoon
AU - Ryu, Kyungho
AU - Park, Jung Hyun
AU - Jung, Seongook
PY - 2018/6/1
Y1 - 2018/6/1
N2 - In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators operating in parallel. In addition, to improve process variation robustness, a precise eight-phase generator consisting of an accurate reference generator and a phase generator with dual-loop calibration (CAL) is proposed, and a phase error of less than 1.21° is achieved. Dynamic and static CAL techniques are also adopted in the edge vernier. A prototype chip having eight channels is fabricated using 0.13-μm CMOS technology. The proposed timing generator has an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.
AB - In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators operating in parallel. In addition, to improve process variation robustness, a precise eight-phase generator consisting of an accurate reference generator and a phase generator with dual-loop calibration (CAL) is proposed, and a phase error of less than 1.21° is achieved. Dynamic and static CAL techniques are also adopted in the edge vernier. A prototype chip having eight channels is fabricated using 0.13-μm CMOS technology. The proposed timing generator has an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.
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U2 - 10.1109/TVLSI.2018.2801030
DO - 10.1109/TVLSI.2018.2801030
M3 - Article
VL - 26
SP - 1015
EP - 1025
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 6
ER -