All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate

Dong Hoon Jung; Kyungho Ryu; Jung Hyun Park; Seong Ook Jung

doi:10.1109/TVLSI.2018.2801030

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate

Dong Hoon Jung, Kyungho Ryu, Jung Hyun Park, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators operating in parallel. In addition, to improve process variation robustness, a precise eight-phase generator consisting of an accurate reference generator and a phase generator with dual-loop calibration (CAL) is proposed, and a phase error of less than 1.21° is achieved. Dynamic and static CAL techniques are also adopted in the edge vernier. A prototype chip having eight channels is fabricated using 0.13-μm CMOS technology. The proposed timing generator has an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm².

Original language	English
Pages (from-to)	1015-1025
Number of pages	11
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	26
Issue number	6
DOIs	https://doi.org/10.1109/TVLSI.2018.2801030
Publication status	Published - 2018 Jun

Bibliographical note

Funding Information:
Manuscript received September 14, 2017; revised December 8, 2017; accepted January 13, 2018. Date of publication February 14, 2018; date of current version May 22, 2018. This work was supported by the IT R&D program of MKE/KEIT (10034834, development of ASIC chip for next-generation high-speed ATE). (Corresponding author: Seong-Ook Jung.) D.-H. Jung and K. Ryu were with the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea. They are now with Samsung Electronics Co., Ltd., Yongin 446-711, South Korea.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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title = "All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and maximum 1.2-GHz test rate",

abstract = "In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing clock frequency. In order to increase the testing clock frequency, a channel of the proposed timing generator consists of four subtiming generators operating in parallel. In addition, to improve process variation robustness, a precise eight-phase generator consisting of an accurate reference generator and a phase generator with dual-loop calibration (CAL) is proposed, and a phase error of less than 1.21° is achieved. Dynamic and static CAL techniques are also adopted in the edge vernier. A prototype chip having eight channels is fabricated using 0.13-μm CMOS technology. The proposed timing generator has an arbitrary test cycle frequency of up to 1.2 GHz, a timing resolution of 1.95 ps, a power consumption of 90 mW, and an area of 1.5 mm2.",

author = "Jung, {Dong Hoon} and Kyungho Ryu and Park, {Jung Hyun} and Jung, {Seong Ook}",

note = "Funding Information: Manuscript received September 14, 2017; revised December 8, 2017; accepted January 13, 2018. Date of publication February 14, 2018; date of current version May 22, 2018. This work was supported by the IT R&D program of MKE/KEIT (10034834, development of ASIC chip for next-generation high-speed ATE). (Corresponding author: Seong-Ook Jung.) D.-H. Jung and K. Ryu were with the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea. They are now with Samsung Electronics Co., Ltd., Yongin 446-711, South Korea.",

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N1 - Funding Information: Manuscript received September 14, 2017; revised December 8, 2017; accepted January 13, 2018. Date of publication February 14, 2018; date of current version May 22, 2018. This work was supported by the IT R&D program of MKE/KEIT (10034834, development of ASIC chip for next-generation high-speed ATE). (Corresponding author: Seong-Ook Jung.) D.-H. Jung and K. Ryu were with the School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea. They are now with Samsung Electronics Co., Ltd., Yongin 446-711, South Korea.

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