In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium-gallium-zinc-oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium-tin-oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A·cm-2, a high on-off current ratio of 106, and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate.
Bibliographical noteFunding Information:
This work was supported by a grant from the Center for Advanced Soft Electronics (CASE) under the Global Frontier Research Program (2013M3A6A5073177) and the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2017R1A2B2005790, 2017R1A4A1015400, and 2017R1E1A1A01077189).
© Copyright 2019 American Chemical Society.
All Science Journal Classification (ASJC) codes
- Materials Science(all)
- Physics and Astronomy(all)