All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics

Dong Un Lim, Seungbeom Choi, Seongchan Kim, Young Jin Choi, Sungjoo Lee, Moon Sung Kang, Yong Hoon Kim, Jeong Ho Cho

Research output: Contribution to journalArticle

1 Citation (Scopus)


In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium-gallium-zinc-oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium-tin-oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A·cm-2, a high on-off current ratio of 106, and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate.

Original languageEnglish
Pages (from-to)8213-8221
Number of pages9
JournalACS Nano
Issue number7
Publication statusPublished - 2019 Jul 23

All Science Journal Classification (ASJC) codes

  • Materials Science(all)
  • Engineering(all)
  • Physics and Astronomy(all)

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  • Cite this

    Lim, D. U., Choi, S., Kim, S., Choi, Y. J., Lee, S., Kang, M. S., Kim, Y. H., & Cho, J. H. (2019). All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics. ACS Nano, 13(7), 8213-8221.