An 11 b 7 ps resolution two-step time-to-digital converter with 3-D vernier space

Yeomyung Kim, Tae Wook Kim

Research output: Contribution to journalArticle

31 Citations (Scopus)

Abstract

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-μ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ± 1.5 LSB, a power consumption of 328.8 7mu; W, and a die area of 0.28 mm2.

Original languageEnglish
Article number6747404
Pages (from-to)2326-2336
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number8
DOIs
Publication statusPublished - 2014 Aug

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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