An 11 b 7 ps resolution two-step time-to-digital converter with 3-D vernier space

Yeomyung Kim, tae wook Kim

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-μ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ± 1.5 LSB, a power consumption of 328.8 7mu; W, and a die area of 0.28 mm2.

Original languageEnglish
Article number6747404
Pages (from-to)2326-2336
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number8
DOIs
Publication statusPublished - 2014 Jan 1

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Electric delay lines
Error correction
Redundancy
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{f0ea2d0b2aad44b78ebf82adc29cfc4a,
title = "An 11 b 7 ps resolution two-step time-to-digital converter with 3-D vernier space",
abstract = "This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-μ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ± 1.5 LSB, a power consumption of 328.8 7mu; W, and a die area of 0.28 mm2.",
author = "Yeomyung Kim and Kim, {tae wook}",
year = "2014",
month = "1",
day = "1",
doi = "10.1109/TCSI.2014.2304656",
language = "English",
volume = "61",
pages = "2326--2336",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "8",

}

An 11 b 7 ps resolution two-step time-to-digital converter with 3-D vernier space. / Kim, Yeomyung; Kim, tae wook.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 8, 6747404, 01.01.2014, p. 2326-2336.

Research output: Contribution to journalArticle

TY - JOUR

T1 - An 11 b 7 ps resolution two-step time-to-digital converter with 3-D vernier space

AU - Kim, Yeomyung

AU - Kim, tae wook

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-μ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ± 1.5 LSB, a power consumption of 328.8 7mu; W, and a die area of 0.28 mm2.

AB - This paper presents a fine-resolution time-to-digital converter (TDC) with a large dynamic range using a 3-D Vernier space. Despite the wide dynamic range, the required delay cells in the delay-lines are minimized, leading to better power efficiency. The proposed TDC also exploits the redundancy and error-correction technique to solve the offset error of coarse conversion in the 3-D Vernier space architecture. The TDC is implemented using a 0.13-μ m CMOS process. The measurement result shows a dynamic range with an 11-bit 6.98-ps resolution, an integrated nonlinearity of ± 1.5 LSB, a power consumption of 328.8 7mu; W, and a die area of 0.28 mm2.

UR - http://www.scopus.com/inward/record.url?scp=84905374952&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84905374952&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2014.2304656

DO - 10.1109/TCSI.2014.2304656

M3 - Article

VL - 61

SP - 2326

EP - 2336

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-8328

IS - 8

M1 - 6747404

ER -