An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13- μm CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB Ω transimpedance gain, 5.9-GHz bandwidth, - 3.2-dBm optical sensitivity for 10 -12 BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm2.
Bibliographical noteFunding Information:
Manuscript received April 14, 2010; revised July 16, 2010; accepted August 09, 2010. Date of publication October 14, 2010; date of current version December 03, 2010. This paper was approved by Guest Editor Jae-Yoon Sim. This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) Grant funded by the Korea government (MEST) (2010-0001557). D. Lee and G. Han are with Yonsei University, Seoul, Korea. J. Han and S. M. Park are with the Ewha Womans University, Seoul, Korea (e-mail: email@example.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2010.2077050
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering