An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer

Dongmyung Lee, Jungwon Han, Gunhee Han, Sung Min Park

Research output: Contribution to journalArticle

68 Citations (Scopus)

Abstract

An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13- μm CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB Ω transimpedance gain, 5.9-GHz bandwidth, - 3.2-dBm optical sensitivity for 10 -12 BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm2.

Original languageEnglish
Article number5599945
Pages (from-to)2861-2873
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number12
DOIs
Publication statusPublished - 2010 Dec 1

Fingerprint

Integrated optoelectronics
Equalizers
Optoelectronic devices
Photodiodes
Bandwidth
Silicon
Operational amplifiers
Optical communication
Energy dissipation
Networks (circuits)
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "An 8.5-Gb/s single-chip optoelectronic integrated circuit (OEIC) for short-distance optical communications is realized in a 0.13- μm CMOS process. The OEIC consists of an on-chip silicon photodiode, a transimpedance amplifier with modified regulated cascode input configuration, an adaptive equalizer based upon slope-detection algorithm, and a limiting amplifier with merged negative impedance circuits. The proposed slope-detection adaptive equalizer compensates the limited bandwidth and the temperature variation of the integrated silicon photodiode. Measured results demonstrate 120-dB Ω transimpedance gain, 5.9-GHz bandwidth, - 3.2-dBm optical sensitivity for 10 -12 BER, and 47-mW power dissipation from a single 1.5-V supply. The OEIC chip core occupies the area of 0.1 mm2.",
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An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer. / Lee, Dongmyung; Han, Jungwon; Han, Gunhee; Park, Sung Min.

In: IEEE Journal of Solid-State Circuits, Vol. 45, No. 12, 5599945, 01.12.2010, p. 2861-2873.

Research output: Contribution to journalArticle

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