An 8Gb multi-level NAND flash memory is fabricated in a 63nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02μm2 and 133mm2, respectively. Performance improves to 4.4MB/S by using the 2x program mode and by decreasing the cycle time from 50ns to 30ns. This also improves the read throughput to 23MB/S.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|Publication status||Published - 2005|
|Event||2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States|
Duration: 2005 Feb 6 → 2005 Feb 10
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering