An 8Gb multi-level NAND flash memory with 63nm STI CMOS process technology

Dae Seok Byeon, Sung Soo Lee, Young Ho Lim, Jin Sung Park, Wook Kee Han, Pan Suk Kwak, Dong Hwan Kim, Dong Hyuk Chae, Seung Hyun Moon, Seung Jae Lee, Hyun Chul Cho, Jung Woo Lee, Moo Sung Kim, Joon Sung Yang, Young Woo Park, Duk Won Bae, Jung Dal Choi, Sung Hoi Hur, Kang Deog Suh

Research output: Contribution to journalConference article

23 Citations (Scopus)
Original languageEnglish
Pages (from-to)46-47
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume48
Publication statusPublished - 2005 Dec 6
Event2005 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 2005 Feb 62005 Feb 10

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Byeon, D. S., Lee, S. S., Lim, Y. H., Park, J. S., Han, W. K., Kwak, P. S., Kim, D. H., Chae, D. H., Moon, S. H., Lee, S. J., Cho, H. C., Lee, J. W., Kim, M. S., Yang, J. S., Park, Y. W., Bae, D. W., Choi, J. D., Hur, S. H., & Suh, K. D. (2005). An 8Gb multi-level NAND flash memory with 63nm STI CMOS process technology. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 48, 46-47.