An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

Kwangho Lee; Hyojun Kim; Woosong Jung; Jinhyung Lee; Haram Ju; Kwanseo Park; Ook Kim; Deog Kyoon Jeong

doi:10.1109/TCSII.2020.3014925

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

Kwangho Lee, Hyojun Kim, Woosong Jung, Jinhyung Lee, Haram Ju, Kwanseo Park, Ook Kim, Deog Kyoon Jeong

School of System & Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

This brief presents the design of a low-power receiver (RX) with an adaptive equalizer and an offset cancellation scheme. The proposed adaptive offset cancellation (AOC) engine removes the random DC offset of the data path by examining the sampled data and edge outputs of a random data stream. In addition, a shared-summer decision-feedback equalizer in a half-rate structure is incorporated to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm2. Thanks to the AOC engine, the proposed RX achieves the BER of less than 10^{-12} in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with 27-dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB.

Original language	English
Article number	9162140
Pages (from-to)	622-626
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	68
Issue number	2
DOIs	https://doi.org/10.1109/TCSII.2020.3014925
Publication status	Published - 2021 Feb

Bibliographical note

Funding Information:
This work was supported in part by the Inter-University Semiconductor Research Center of Seoul National University and in part by the Inchips Technologies, South Korea

Funding Information:
Manuscript received May 27, 2020; revised July 2, 2020; accepted August 2, 2020. Date of publication August 7, 2020; date of current version January 29, 2021. This work was supported in part by the Inter-University Semiconductor Research Center of Seoul National University and in part by the Inchips Technologies, South Korea. This brief was recommended by Associate Editor Y. Pu. (Corresponding author: Deog-Kyoon Jeong.) Kwangho Lee, Hyojun Kim, Woosong Jung, and Deog-Kyoon Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the InterUniversity Semiconductor Research Center, College of Engineering, Seoul National University, Seoul 08826, South Korea (e-mail: khlee@isdl.snu.ac.kr; dkjeong@snu.ac.kr). Jinhyung Lee is with SK. Hynix, Icheon 17336, South Korea.

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2020.3014925

Cite this

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title = "An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS",

abstract = "This brief presents the design of a low-power receiver (RX) with an adaptive equalizer and an offset cancellation scheme. The proposed adaptive offset cancellation (AOC) engine removes the random DC offset of the data path by examining the sampled data and edge outputs of a random data stream. In addition, a shared-summer decision-feedback equalizer in a half-rate structure is incorporated to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm2. Thanks to the AOC engine, the proposed RX achieves the BER of less than 10^{-12} in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with 27-dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB.",

author = "Kwangho Lee and Hyojun Kim and Woosong Jung and Jinhyung Lee and Haram Ju and Kwanseo Park and Ook Kim and Jeong, {Deog Kyoon}",

note = "Funding Information: This work was supported in part by the Inter-University Semiconductor Research Center of Seoul National University and in part by the Inchips Technologies, South Korea Funding Information: Manuscript received May 27, 2020; revised July 2, 2020; accepted August 2, 2020. Date of publication August 7, 2020; date of current version January 29, 2021. This work was supported in part by the Inter-University Semiconductor Research Center of Seoul National University and in part by the Inchips Technologies, South Korea. This brief was recommended by Associate Editor Y. Pu. (Corresponding author: Deog-Kyoon Jeong.) Kwangho Lee, Hyojun Kim, Woosong Jung, and Deog-Kyoon Jeong are with the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea, and also with the InterUniversity Semiconductor Research Center, College of Engineering, Seoul National University, Seoul 08826, South Korea (e-mail: khlee@isdl.snu.ac.kr; dkjeong@snu.ac.kr). Jinhyung Lee is with SK. Hynix, Icheon 17336, South Korea. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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N2 - This brief presents the design of a low-power receiver (RX) with an adaptive equalizer and an offset cancellation scheme. The proposed adaptive offset cancellation (AOC) engine removes the random DC offset of the data path by examining the sampled data and edge outputs of a random data stream. In addition, a shared-summer decision-feedback equalizer in a half-rate structure is incorporated to reduce power dissipation and hardware complexity of the adaptive equalizer. A prototype chip fabricated in 40 nm CMOS technology occupies an active area of 0.083 mm2. Thanks to the AOC engine, the proposed RX achieves the BER of less than 10^{-12} in a wide range of data rates: 1.62-10 Gb/s. The proposed RX consumes 18.6 mW at 10 Gb/s over a channel with 27-dB loss at 5 GHz, exhibiting a figure-of-merit of 0.068 pJ/b/dB.

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An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS

Abstract

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