3D die stacking integration technology offers a feasible and promising solution to overcome the barriers of interconnect efficiency and device scaling in modern systems. The emerging trend from 2D IC to 3D IC obtains better performance by getting more silicon area and shortening wire length. In 3D integration technologies, different layers of active devices are connected through vertical links. Currently, TSV is the most popular and practical way to implement vertical links. Yet, there exist difficulties at the technological level ensuring an acceptable yield number of vertical links. Therefore, the bandwidth of vertical links is often made smaller than horizontal links, which becomes a bottleneck of the whole system. This paper presents a traffic distributing adaptive routing algorithm for 3D systems with limited bandwidth in vertical links. Our simulation with synthetic traffic pattern reveals that in a 4x4x4 3D mesh network architecture, our proposed algorithm can achieve significant performance improvement in network latency and throughput compared to existing routing algorithms and is robust in that the performance is stable under different traffic patterns.
|Title of host publication||2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012|
|Publisher||IEEE Computer Society|
|Number of pages||6|
|Publication status||Published - 2015 Nov 18|
|Event||IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012 - Santa Cruz, United States|
Duration: 2012 Oct 7 → 2012 Oct 10
|Name||IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC|
|Conference||IEEE/IFIP 20th International Conference on VLSI and System-on-Chip, VLSI-SoC 2012|
|Period||12/10/7 → 12/10/10|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. 2012-0006272) and Ministry of Knowledge Economy (MKE) and IDEC Platform Center (IPC) at Hanyang Univ.
© 2012 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering