An advanced BIRA for memories with an optimal repair rate and fast analysis speed by using a branch analyzer

Woosik Jeong, Joohwan Lee, Taewoo Han, Kaangchil Lee, Sungho Kang

Research output: Contribution to journalArticle

35 Citations (Scopus)

Abstract

As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.

Original languageEnglish
Article number5621043
Pages (from-to)2014-2026
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume29
Issue number12
DOIs
Publication statusPublished - 2010 Dec 1

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Redundancy
Repair
Data storage equipment
Hardware
Defects

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

@article{b53d8dc7303141118f7d62f1a4c18a83,
title = "An advanced BIRA for memories with an optimal repair rate and fast analysis speed by using a branch analyzer",
abstract = "As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.",
author = "Woosik Jeong and Joohwan Lee and Taewoo Han and Kaangchil Lee and Sungho Kang",
year = "2010",
month = "12",
day = "1",
doi = "10.1109/TCAD.2010.2062830",
language = "English",
volume = "29",
pages = "2014--2026",
journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",
issn = "0278-0070",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

An advanced BIRA for memories with an optimal repair rate and fast analysis speed by using a branch analyzer. / Jeong, Woosik; Lee, Joohwan; Han, Taewoo; Lee, Kaangchil; Kang, Sungho.

In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 12, 5621043, 01.12.2010, p. 2014-2026.

Research output: Contribution to journalArticle

TY - JOUR

T1 - An advanced BIRA for memories with an optimal repair rate and fast analysis speed by using a branch analyzer

AU - Jeong, Woosik

AU - Lee, Joohwan

AU - Han, Taewoo

AU - Lee, Kaangchil

AU - Kang, Sungho

PY - 2010/12/1

Y1 - 2010/12/1

N2 - As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.

AB - As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.

UR - http://www.scopus.com/inward/record.url?scp=78649342725&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78649342725&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2010.2062830

DO - 10.1109/TCAD.2010.2062830

M3 - Article

AN - SCOPUS:78649342725

VL - 29

SP - 2014

EP - 2026

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 12

M1 - 5621043

ER -