An advanced BIRA using parallel sub-analyzers for embedded memories

Woosik Jeong, Taewoo Han, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.

Original languageEnglish
Title of host publication2009 International SoC Design Conference, ISOCC 2009
Pages249-252
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International SoC Design Conference, ISOCC 2009 - Busan, Korea, Republic of
Duration: 2009 Nov 222009 Nov 24

Other

Other2009 International SoC Design Conference, ISOCC 2009
CountryKorea, Republic of
CityBusan
Period09/11/2209/11/24

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Jeong, W., Han, T., & Kang, S. (2009). An advanced BIRA using parallel sub-analyzers for embedded memories. In 2009 International SoC Design Conference, ISOCC 2009 (pp. 249-252). [5423810] https://doi.org/10.1109/SOCDC.2009.5423810