TY - GEN
T1 - An advanced BIRA using parallel sub-analyzers for embedded memories
AU - Jeong, Woosik
AU - Han, Taewoo
AU - Kang, Sungho
PY - 2009
Y1 - 2009
N2 - Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.
AB - Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.
UR - http://www.scopus.com/inward/record.url?scp=77951431704&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77951431704&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2009.5423810
DO - 10.1109/SOCDC.2009.5423810
M3 - Conference contribution
AN - SCOPUS:77951431704
SN - 9781424450343
T3 - 2009 International SoC Design Conference, ISOCC 2009
SP - 249
EP - 252
BT - 2009 International SoC Design Conference, ISOCC 2009
T2 - 2009 International SoC Design Conference, ISOCC 2009
Y2 - 22 November 2009 through 24 November 2009
ER -