An advanced filtering TLB for low power consumption

Jin Hyuck Choi, Jung Hoon Lee, Gi Ho Park, Shin Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This research is to design a new two-level TLB (translation look-aside buffer) architecture that integrates a 2-way banked filter TLB with a 2-way banked main TLB. One of the main objectives is to reduce power consumption in embedded processors by distributing the accesses to the TLB entries across several banks in a balanced manner. Thus, an advanced filtering technique is devised to reduce power dissipation by adopting a sub-bank structure at the filter TLB. And also a bank-associative structure is applied to each level of the TLB hierarchy. Simulation result shows that the miss ratio and Energy∗Delay product can be improved by 59.26% and 24.9%, respectively, compared with a micro TLB with 4-32 entries, and 40.81% and 12.18%, compared with a micro TLB with 16-32 entries.

Original languageEnglish
Title of host publicationProceedings - 14th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2002
EditorsClaudio L. de Amorim, Alberto Ferreira De Souza, Neyval Costa Reis
PublisherIEEE Computer Society
Pages93-99
Number of pages7
ISBN (Electronic)0769517722
DOIs
Publication statusPublished - 2002
Event14th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2002 - Vitoria, Brazil
Duration: 2002 Oct 282002 Oct 30

Publication series

NameProceedings - Symposium on Computer Architecture and High Performance Computing
Volume2002-January
ISSN (Print)1550-6533

Other

Other14th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2002
CountryBrazil
CityVitoria
Period02/10/2802/10/30

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software

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