This research is to design a new two-level TLB (translation look-aside buffer) architecture that integrates a 2-way banked filter TLB with a 2-way banked main TLB. One of the main objectives is to reduce power consumption in embedded processors by distributing the accesses to the TLB entries across several banks in a balanced manner. Thus, an advanced filtering technique is devised to reduce power dissipation by adopting a sub-bank structure at the filter TLB. And also a bank-associative structure is applied to each level of the TLB hierarchy. Simulation result shows that the miss ratio and Energy∗Delay product can be improved by 59.26% and 24.9%, respectively, compared with a micro TLB with 4-32 entries, and 40.81% and 12.18%, compared with a micro TLB with 16-32 entries.
|Title of host publication||Proceedings - 14th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2002|
|Editors||Claudio L. de Amorim, Alberto Ferreira De Souza, Neyval Costa Reis|
|Publisher||IEEE Computer Society|
|Number of pages||7|
|Publication status||Published - 2002|
|Event||14th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2002 - Vitoria, Brazil|
Duration: 2002 Oct 28 → 2002 Oct 30
|Name||Proceedings - Symposium on Computer Architecture and High Performance Computing|
|Other||14th Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2002|
|Period||02/10/28 → 02/10/30|
Bibliographical notePublisher Copyright:
© 2002 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture