This paper presents a 4× compressive CMOS imager for always-on operation that achieves an energy efficiency of 51pJ/pixel, while maintaining high image quality of PSNR>32dB and SSIM>0.84. This is enabled by an energy-efficient compressive-sensing (CS) encoder, which replaces a densely populated CS encoding method with a highly sparse pseudo-diagonal one. Since the proposed CS encoder can be implemented with an energy-efficient switched-capacitor matrix multiplier at pixel outputs, data compression is achieved prior to pixel digitization, thereby greatly reducing ADC power, data size, and I/O power. The energy efficiency of the imager is further improved by incorporating it into dynamic single-slope ADCs. A prototype VGA imager consumes only 0.7mW at 45 fps. The corresponding energy per pixel (51pJ/pixel) amounts to a 20× improvement over the previous low-energy benchmark on CS imagers.
|Title of host publication||2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2020 Jun|
|Event||2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States|
Duration: 2020 Jun 16 → 2020 Jun 19
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020|
|Period||20/6/16 → 20/6/19|
Bibliographical notePublisher Copyright:
© 2020 IEEE.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering