The growing capacity and density of embedded memories increases the probability of defects and affects the yield. To improve the yield, built-in redundancy analysis (BIRA) has been developed to replace faulty cells with healthy redundant cells. BIRA requires a high repair rate and a feasible hardware size for implementation. Although many BIRAs have been proposed, most of them still demonstrate a low repair rate or a large required hardware size. The proposed BIRA employs an intuitive algorithm with a small-area analyzer that uses 1-D spare segments in the 2-D spare structure. Because most faults in the memory are single faults, spare segments can be used to efficiently allocate redundancies. In terms of the yield, 1-D spare segments are effective when used with an intuitive algorithm that can be implemented with a small hardware overhead. Experimental results show that the proposed BIRA has a higher repair rate and relatively low hardware overhead than state-of-the-art BIRAs and has the advantages of 1-D spare segments.
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2018 Jan|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering